Expose FIRRTL asClock construct

Additionally, fix Clock.asUInt (previously, it threw an esoteric exception), and add a simple test of both.

3 files changed, 10 insertions, 1 deletions

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
index 77a31252..d7464efa 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
@@ -699,6 +699,11 @@ sealed class Bool(dir: Direction, lit: Option[ULit] = None) extends UInt(dir, Wi
   def && (that: Bool): Bool = macro SourceInfoTransform.thatArg
 
   def do_&& (that: Bool)(implicit sourceInfo: SourceInfo): Bool = this & that
+
+  /** Reinterprets this Bool as a Clock.  */
+  def asClock(): Clock = macro SourceInfoTransform.noArg
+
+  def do_asClock(implicit sourceInfo: SourceInfo): Clock = pushOp(DefPrim(sourceInfo, Clock(), AsClockOp, ref))
 }
 
 object Bool {
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Data.scala b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
index 573632ab..197b6181 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Data.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
@@ -5,9 +5,10 @@ package chisel3.core
 import scala.language.experimental.macros
 
 import chisel3.internal._
-import chisel3.internal.Builder.pushCommand
+import chisel3.internal.Builder.{pushCommand, pushOp}
 import chisel3.internal.firrtl._
 import chisel3.internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, UnlocatableSourceInfo, WireTransform, SourceInfoTransform}
+import chisel3.internal.firrtl.PrimOp.AsUIntOp
 
 sealed abstract class Direction(name: String) {
   override def toString: String = name
@@ -177,4 +178,6 @@ sealed class Clock(dirArg: Direction) extends Element(dirArg, Width(1)) {
 
   /** Not really supported */
   def toPrintable: Printable = PString("CLOCK")
+
+  override def do_asUInt(implicit sourceInfo: SourceInfo): UInt = pushOp(DefPrim(sourceInfo, UInt(this.width), AsUIntOp, ref))
 }
diff --git a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
index e39b007e..0641686c 100644
--- a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
@@ -42,6 +42,7 @@ object PrimOp {
   val ConvertOp = PrimOp("cvt")
   val AsUIntOp = PrimOp("asUInt")
   val AsSIntOp = PrimOp("asSInt")
+  val AsClockOp = PrimOp("asClock")
 }
 
 abstract class Arg {