| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2016-08-25 | fix a bug in setModName | Donggyu Kim | |
| 2016-08-25 | Use bulkConnect in Vec,fill if any (flattened) element of the Vec has a ↵ | Jim Lawson | |
| direction associated with it. This impetus for this came out of discussion during the chisel meeting of 8/24/16 in response to errors running the chisel tutorial examples Adder test. | |||
| 2016-08-24 | Per Chisel meeting. | chick | |
| signalName -> instanceName SignalId -> InstanceId Based on Stephen's comments on PR | |||
| 2016-08-23 | Swap name of compileOption "assumeNoDirectionIsOutput" to ↵ | Jim Lawson | |
| "assumeNoDirectionIsInput". | |||
| 2016-08-22 | Purely cosmetic changes to placate the scalastyle checker. | Jim Lawson | |
| 2016-08-22 | Fix firrtlDirection for class DeqIO. | Jim Lawson | |
| 2016-08-21 | AnnotatingExample: | chick | |
| Removed extraneous logic Renamed doStuff to buildAnnotatedCircuit Removed println's | |||
| 2016-08-21 | Add AnnotationSpec file which provides an example of a way to implement ↵ | chick | |
| generation of annotations in a chisel circuit that could be used by custom firrtl passes This spec also shows and tests in a limited way the new API of .signalName, .pathName, parentModName which allows access to the various path information of a chisel component (something that subclasses SignalId, most prominently SubClasses of Data and Module | |||
| 2016-08-21 | Add annotating example to test new signal name api | chick | |
| 2016-08-21 | provides signal name methods for firrtl annotation and chisel testers | Donggyu Kim | |
| * signalName: returns the chirrtl name of the signal * pathName: returns the full path name of the signal from the top module * parentPathName: returns the full path of the signal's parent module instance from the top module * parentModName: returns the signal's parent **module(not instance)** name. | |||
| 2016-08-19 | Restore immutability of direction overrides. | Jim Lawson | |
| Input, Output, and Flipped clone their inputs. | |||
| 2016-08-19 | Simplify autioIOWrap code in computePorts(). | Jim Lawson | |
| As a side-effect, handle BlackBoxes correctly. | |||
| 2016-08-18 | Add assumeNoDirectionIsOutput. | Jim Lawson | |
| 2016-08-18 | Use isFirrtlFlipped() to determine port direction. | Jim Lawson | |
| 2016-08-18 | Merge branch 'sdtwigg_connectwrap_renamechisel3' into gsdt_tests | Jim Lawson | |
| Revive support for firrtl flip direction. Remove compileOptions.internalConnectionToInputOk | |||
| 2016-08-17 | Rocket-chip updates. | Jim Lawson | |
| Assume LHSItOutput if neither side is driving. Restore Wire()'s removal of direction in binding. | |||
| 2016-08-17 | Reduce rocket-chip elaboration errors. | Jim Lawson | |
| 2016-08-16 | Add component to signature. | Jim Lawson | |
| 2016-08-16 | Provide public SignalID trait to be used to conjure up a signal identifier. | Jim Lawson | |
| 2016-08-16 | Merge branch 'master' into sdtwigg_connectwrap_renamechisel3 | Jim Lawson | |
| 2016-08-15 | Make "def width" a private API; expose isWidthKnown instead (#257) | Andrew Waterman | |
| * Make "def width" a private API; expose isWidthKnown instead Resolves #256. Since width was used to determine whether getWidth would succeed, I added def isWidthKnown: Boolean but another option would be to expose something like def widthOption: Option[Int] ...thoughts? * Document getWidth/isWidthKnown * Add widthOption for more idiomatic Scala manipulation of widths | |||
| 2016-08-12 | Use compileOptions to determine if Missing...FieldExceptions are thrown. | Jim Lawson | |
| 2016-08-12 | Merge branch 'compile_options' into sdtwigg_connectwrap_renamechisel3 | Jim Lawson | |
| 2016-08-12 | Add support for per-Module compilation options. | Jim Lawson | |
| Nothing uses these now, but when we integrate Stephen's PR200, we'll need a way to selectively enable some strict connection checks on a file by file basis. We plan to do this using package imports which will define suitable compilation options. | |||
| 2016-08-11 | Merge branch 'master' into sdtwigg_connectwrap_renamechisel3 | Jim Lawson | |
| 2016-08-09 | Support Module name overrides with "override def desiredName" | Andrew Waterman | |
| The API allowed this before, but not safely, as users could create name conflicts. This exposes the pre-deduplication/sanitization naming API, and closes the other one. | |||
| 2016-08-09 | Legalize identifier names before printing | Andrew Waterman | |
| It's not entirely clear what the FIRRTL implementation supports, so I'm using the ANSI C requirements for the time being. | |||
| 2016-08-09 | counter(inc,n) example should reflect actual use (#252) | Colin Schmidt | |
| 2016-08-04 | Deal with directions on Clocks. | Jim Lawson | |
| 2016-08-03 | Merge branch 'master' into sdtwigg_connectwrap_renamechisel3 | Jim Lawson | |
| 2016-08-03 | Merge "package" code into "compatibility". | Jim Lawson | |
| 2016-07-31 | Remove deprecated FileSystemUtilities | Andrew Waterman | |
| This has been deprecated for a long time now (and really shouldn't have existed to begin with). | |||
| 2016-07-31 | Expose asUInt from Data | Andrew Waterman | |
| Deprecating toBits removes the capability to cast an arbitrary type to UInt. While it's still possible to do so using asBits.asUInt, this creates boilerplate. (asBits is almost never useful itself.) | |||
| 2016-07-31 | Fix two deprecation warnings | Andrew Waterman | |
| 2016-07-28 | Add missing Decoupled object pointer. | Jim Lawson | |
| 2016-07-28 | Add missing factory constructors. | Jim Lawson | |
| 2016-07-27 | More compatibility fixes | Jim Lawson | |
| 2016-07-27 | Correct EnqIO/DeqIO Flipped-ness. | Jim Lawson | |
| 2016-07-27 | Correct EnqIO/DeqIO Flipped-ness. | Jim Lawson | |
| 2016-07-27 | Additional compatibility code. | Jim Lawson | |
| 2016-07-27 | Correct EnqIO/DeqIO Flipped-ness. | Jim Lawson | |
| 2016-07-27 | Correct EnqIO/DeqIO Flipped-ness. | Jim Lawson | |
| 2016-07-26 | Add ValidIO definition for old code. | Jim Lawson | |
| 2016-07-25 | Enable current (chisel2-style) compatibility mode. | Jim Lawson | |
| 2016-07-25 | Minimize differences with master. | Jim Lawson | |
| Remove .Lit(x) usage. Undo "private" scope change. Change "firing" back to "fire". Add package level NODIR definition. | |||
| 2016-07-25 | Merge branch 'master' into sdtwigg_connectwrap_renamechisel3 | Jim Lawson | |
| 2016-07-25 | Use more idiomatic ScalaTest exception expecting code. | Jim Lawson | |
| 2016-07-25 | Add missing compatibility.scala. | Jim Lawson | |
| 2016-07-25 | catch Bad connection exception | Jim Lawson | |
| 2016-07-21 | Introduce chiselCloneType to distinguish from cloneType. | Jim Lawson | |
| Still fails one test - DirectionSpec in Direction.scala | |||
 |
index : chiselX | |
| Chisel with SFC compatibility |
| summaryrefslogtreecommitdiff |