summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorJim Lawson2016-07-25 09:19:14 -0700
committerJim Lawson2016-07-25 09:19:14 -0700
commit50518f43cbd9c783633714a26ecdb0f2f18a1142 (patch)
tree42cd994067ce268195cd64f9da653baa36b6085f
parent2d4cb434f214c31b5e3e4247775b27f1eb8d7734 (diff)
Use more idiomatic ScalaTest exception expecting code.
-rw-r--r--src/main/scala/chisel3/package.scala1
-rw-r--r--src/test/scala/chiselTests/Direction.scala13
2 files changed, 4 insertions, 10 deletions
diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index e43434c0..d47ed890 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -113,4 +113,5 @@ package object chisel3 {
val INPUT = chisel3.core.Direction.Input
val OUTPUT = chisel3.core.Direction.Output
+ type ChiselException = chisel3.internal.ChiselException
}
diff --git a/src/test/scala/chiselTests/Direction.scala b/src/test/scala/chiselTests/Direction.scala
index bb01f0eb..2fe31475 100644
--- a/src/test/scala/chiselTests/Direction.scala
+++ b/src/test/scala/chiselTests/Direction.scala
@@ -22,7 +22,7 @@ class BadDirection extends DirectionHaver {
io.in := UInt.Lit(0)
}
-class DirectionSpec extends ChiselPropSpec {
+class DirectionSpec extends ChiselPropSpec with ShouldMatchers {
//TODO: In Chisel3 these are actually FIRRTL errors. Remove from tests?
@@ -31,15 +31,8 @@ class DirectionSpec extends ChiselPropSpec {
}
property("Inputs should not be assignable") {
- var excepts: Boolean = false
- try elaborate(new BadDirection)
- catch {
- case e: Exception => {
- excepts = true
- }
- // Should except so this is okay
- // Ideally, would throw and catch more precise exception
+ a[ChiselException] should be thrownBy {
+ elaborate(new BadDirection)
}
- assert(excepts, "Bad connection should have thrown exception!")
}
}