diff options
| author | Jim Lawson | 2016-07-27 09:35:02 -0700 |
|---|---|---|
| committer | Jim Lawson | 2016-07-27 09:35:02 -0700 |
| commit | 87d69afd1c8f28d91c78e7a539f6bf7a908e2a1f (patch) | |
| tree | cad3be2a3374ac8b9df77dbbbe3cff52696342bc | |
| parent | e065416d59871d790cca9d75dc9a40fcc7b52015 (diff) | |
Correct EnqIO/DeqIO Flipped-ness.
| -rw-r--r-- | src/main/scala/chisel3/util/Decoupled.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala index 3ee363a2..0d000f49 100644 --- a/src/main/scala/chisel3/util/Decoupled.scala +++ b/src/main/scala/chisel3/util/Decoupled.scala @@ -76,9 +76,9 @@ object DeqIO { class QueueIO[T <: Data](gen: T, entries: Int) extends Bundle { /** I/O to enqueue data, is [[Chisel.DecoupledIO]] flipped */ - val enq = EnqIO(gen) + val enq = DeqIO(gen) /** I/O to enqueue data, is [[Chisel.DecoupledIO]]*/ - val deq = DeqIO(gen) + val deq = EnqIO(gen) /** The current amount of data in the queue */ val count = Output(UInt.width(log2Up(entries + 1))) } |
