Enable current (chisel2-style) compatibility mode.

4 files changed, 83 insertions, 6 deletions

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Binding.scala b/chiselFrontend/src/main/scala/chisel3/core/Binding.scala
index d8d9ebd2..75a80e4f 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Binding.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Binding.scala
@@ -112,17 +112,38 @@ object Binding {
   }
 
   // Excepts if any root element is unbound and thus not on the hardware graph
-  def checkSynthesizable(target: Data, error_prelude: String): Unit =
+  def checkSynthesizable(target: Data, error_prelude: String): Unit = {
+    // This is called is we support autoIOWrap
+    def elementOfIO(element: Data): Boolean = {
+      element._parent match {
+        case None => false
+        case Some(x: Module) => {
+          // io.flatten eliminates Clock elements, so we need to use io.allElements
+          val ports = x.io.allElements
+          val isIOElement = ports.contains(element) || element == x.clock || element == x.reset
+          isIOElement
+        }
+      }
+    }
     try walkToBinding(
       target,
       element => element.binding match {
         case SynthesizableBinding() => {} // OK
-        case binding => throw NotSynthesizableException
+        case binding =>
+          // The following kludge is an attempt to provide backward compatibility
+          // It should be done at at higher level.
+          if (!(autoIOWrap && elementOfIO(element)))
+            throw NotSynthesizableException
+          else
+            Binding.bind(element, PortBinder(element._parent.get), "Error: IO")
       }
     )
     catch {
       case BindingException(message) => throw BindingException(s"$error_prelude$message")
     }
+  }
+  // This should be configure by options in Driver.
+  private[chisel3] var autoIOWrap = true
 }
 
 // Location refers to 'where' in the Module hierarchy this lives
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
index 6ec455ca..ecae7340 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
@@ -521,10 +521,6 @@ private[core] sealed trait UIntFactory {
   def width(width: Int): UInt = apply(Width(width))
   /** Create a UInt port with specified width. */
   def width(width: Width): UInt = new UInt(width)
-  /** Create a UInt with a specified width - compatibility with Chisel2. */
-  def apply(dummy: Option[Direction] = None, width: Int): UInt = apply(Width(width))
-  /** Create a UInt literal with inferred width.- compatibility with Chisel2. */
-  def apply(value: BigInt): UInt = apply(value, Width())
   /** Create a UInt literal with fixed width. */
   def apply(value: BigInt, width: Int): UInt = Lit(value, Width(width))
   /** Create a UInt literal with inferred width. */
@@ -546,6 +542,20 @@ private[core] sealed trait UIntFactory {
     result
   }
 
+  /** Create a UInt with a specified width - compatibility with Chisel2. */
+  def apply(dummy: Option[Direction] = None, width: Int): UInt = apply(Width(width))
+  /** Create a UInt literal with inferred width.- compatibility with Chisel2. */
+  def apply(value: BigInt): UInt = apply(value, Width())
+  /** Create a UInt with a specified direction and width - compatibility with Chisel2. */
+  def apply(direction: Direction, width: Int): UInt = {
+    val result = apply(Width(width))
+    direction match {
+      case Direction.Input => Input(result)
+      case Direction.Output => Output(result)
+      case Direction.Unspecified => result
+    }
+  }
+
   private def parse(n: String) = {
     val (base, num) = n.splitAt(1)
     val radix = base match {
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Data.scala b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
index 9e362fa6..73470383 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Data.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
@@ -16,6 +16,7 @@ sealed abstract class Direction(name: String) {
 object Direction {
   object Input  extends Direction("input") { override def flip: Direction = Output }
   object Output extends Direction("output") { override def flip: Direction = Input }
+  object Unspecified extends Direction("unspecified") { override def flip: Direction = Unspecified }
 }
 
 @deprecated("debug doesn't do anything in Chisel3 as no pruning happens in the frontend", "chisel3")
diff --git a/src/test/scala/chiselTests/IOCompatibility.scala b/src/test/scala/chiselTests/IOCompatibility.scala
new file mode 100644
index 00000000..b904d77e
--- /dev/null
+++ b/src/test/scala/chiselTests/IOCompatibility.scala
@@ -0,0 +1,45 @@
+// See LICENSE for license details.
+
+package chiselTests
+
+import chisel3._
+
+class IOCSimpleIO extends Bundle {
+  val in  = UInt(INPUT,  32)
+  val out = UInt(OUTPUT, 32)
+}
+
+class IOCPlusOne extends Module {
+  val io = new IOCSimpleIO
+  io.out := io.in + UInt(1)
+}
+
+class IOCModuleVec(val n: Int) extends Module {
+  val io = new Bundle {
+    val ins  = Vec(n, UInt(INPUT,  32))
+    val outs = Vec(n, UInt(OUTPUT, 32))
+  }
+  val pluses = Vec.fill(n){ Module(new IOCPlusOne).io }
+  for (i <- 0 until n) {
+    pluses(i).in := io.ins(i)
+    io.outs(i)   := pluses(i).out
+  }
+}
+
+class IOCModuleWire extends Module {
+  val io = new IOCSimpleIO
+  val inc = Wire(Module(new IOCPlusOne).io.chiselCloneType)
+  inc.in := io.in
+  io.out := inc.out
+}
+
+class IOCompatibilitySpec extends ChiselPropSpec {
+
+  property("IOCModuleVec should elaborate") {
+    elaborate { new IOCModuleVec(2) }
+  }
+
+  property("IOCModuleWire should elaborate") {
+    elaborate { new IOCModuleWire }
+  }
+}