Merge branch 'master' into sdtwigg_connectwrap_renamechisel3

4 files changed, 36 insertions, 22 deletions

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
index ba0720a4..bbed4d9f 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
@@ -94,8 +94,11 @@ extends HasId {
   private[core] val _ids = ArrayBuffer[HasId]()
   Builder.currentModule = Some(this)
 
-  /** Name of the instance. */
-  val name = Builder.globalNamespace.name(getClass.getName.split('.').last)
+  /** Desired name of this module. */
+  def desiredName = this.getClass.getName.split('.').last
+
+  /** Legalized name of this module. */
+  final val name = Builder.globalNamespace.name(desiredName)
 
   /** IO for this Module. At the Scala level (pre-FIRRTL transformations),
     * connections in and out of a Module may only go through `io` elements.
diff --git a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
index 168e19b2..cd3e1ca7 100644
--- a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
@@ -21,16 +21,25 @@ private[chisel3] class Namespace(parent: Option[Namespace], keywords: Set[String
     if (this contains tryName) rename(n) else tryName
   }
 
+  private def sanitize(s: String): String = {
+    // TODO what character set does FIRRTL truly support? using ANSI C for now
+    def legalStart(c: Char) = (c >= 'a' && c <= 'z') || (c >= 'A' && c <= 'Z') || c == '_'
+    def legal(c: Char) = legalStart(c) || (c >= '0' && c <= '9')
+    val res = s filter legal
+    if (res.isEmpty || !legalStart(res.head)) s"_$res" else res
+  }
+
   def contains(elem: String): Boolean = {
     names.contains(elem) || parent.map(_ contains elem).getOrElse(false)
   }
 
   def name(elem: String): String = {
-    if (this contains elem) {
-      name(rename(elem))
+    val sanitized = sanitize(elem)
+    if (this contains sanitized) {
+      name(rename(sanitized))
     } else {
-      names(elem) = 1
-      elem
+      names(sanitized) = 1
+      sanitized
     }
   }
 
diff --git a/src/main/scala/chisel3/internal/firrtl/Emitter.scala b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
index 08646cf9..31856541 100644
--- a/src/main/scala/chisel3/internal/firrtl/Emitter.scala
+++ b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
@@ -46,18 +46,21 @@ private class Emitter(circuit: Circuit) {
   }
 
   // Map of Module FIRRTL definition to FIRRTL name, if it has been emitted already.
-  private val defnMap = collection.mutable.HashMap[String, String]()
+  private val defnMap = collection.mutable.HashMap[(String, String), Component]()
   // Map of Component name to FIRRTL id.
   private val moduleMap = collection.mutable.HashMap[String, String]()
 
-  /** Generates the FIRRTL module definition with a specified name.
+  /** Generates the FIRRTL module declaration.
     */
-  private def moduleDefn(m: Component, name: String): String = {
+  private def moduleDecl(m: Component): String = m.id match {
+    case _: BlackBox => newline + s"extmodule ${m.name} : "
+    case _: Module => newline + s"module ${m.name} : "
+  }
+
+  /** Generates the FIRRTL module definition.
+    */
+  private def moduleDefn(m: Component): String = {
     val body = new StringBuilder
-    m.id match {
-      case _: BlackBox => body ++= newline + s"extmodule $name : "
-      case _: Module => body ++= newline + s"module $name : "
-    }
     withIndent {
       for (p <- m.ports)
         body ++= newline + emitPort(p)
@@ -82,21 +85,20 @@ private class Emitter(circuit: Circuit) {
     */
   private def emit(m: Component): String = {
     // Generate the body.
-    val moduleName = m.id.getClass.getName.split('.').last
-    val defn = moduleDefn(m, moduleName)
+    val defn = moduleDefn(m)
 
-    defnMap get defn match {
-      case Some(deduplicatedName) =>
-        moduleMap(m.name) = deduplicatedName
+    defnMap get (m.id.desiredName, defn) match {
+      case Some(duplicate) =>
+        moduleMap(m.name) = duplicate.name
         ""
       case None =>
         require(!(moduleMap contains m.name),
             "emitting module with same name but different contents")
 
         moduleMap(m.name) = m.name
-        defnMap(defn) = m.name
+        defnMap((m.id.desiredName, defn)) = m
 
-        moduleDefn(m, m.name)
+        moduleDecl(m) + defn
     }
   }
 
diff --git a/src/main/scala/chisel3/util/Counter.scala b/src/main/scala/chisel3/util/Counter.scala
index 40615769..1c95190b 100644
--- a/src/main/scala/chisel3/util/Counter.scala
+++ b/src/main/scala/chisel3/util/Counter.scala
@@ -32,8 +32,8 @@ class Counter(val n: Int) {
 /** Counter Object
   * Example Usage:
   * {{{ val countOn = Bool(true) // increment counter every clock cycle
-  * val myCounter = Counter(countOn, n)
-  * when ( myCounter.value === UInt(3) ) { ... } }}}*/
+  * val (myCounterValue, myCounterWrap) = Counter(countOn, n)
+  * when ( myCounterValue === UInt(3) ) { ... } }}}*/
 object Counter
 {
   def apply(n: Int): Counter = new Counter(n)