diff options
Diffstat (limited to 'src/test')
30 files changed, 93 insertions, 69 deletions
diff --git a/src/test/scala/chiselTests/AnnotatingDiamondSpec.scala b/src/test/scala/chiselTests/AnnotatingDiamondSpec.scala index e88d475e..853d82af 100644 --- a/src/test/scala/chiselTests/AnnotatingDiamondSpec.scala +++ b/src/test/scala/chiselTests/AnnotatingDiamondSpec.scala @@ -6,7 +6,7 @@ import chisel3._ import chisel3.experimental.{annotate, ChiselAnnotation, RunFirrtlTransform} import chisel3.internal.InstanceId import chisel3.testers.BasicTester -import firrtl.{CircuitState, LowForm, Transform} +import firrtl.{CircuitForm, CircuitState, LowForm, Transform} import firrtl.annotations.{ Annotation, SingleTargetAnnotation, @@ -19,15 +19,15 @@ import org.scalatest._ * Chisel/Firrtl library */ case class IdentityAnnotation(target: Named, value: String) extends SingleTargetAnnotation[Named] { - def duplicate(n: Named) = this.copy(target = n) + def duplicate(n: Named): IdentityAnnotation = this.copy(target = n) } /** ChiselAnnotation that corresponds to the above FIRRTL annotation */ case class IdentityChiselAnnotation(target: InstanceId, value: String) extends ChiselAnnotation with RunFirrtlTransform { - def toFirrtl = IdentityAnnotation(target.toNamed, value) - def transformClass = classOf[IdentityTransform] + def toFirrtl: IdentityAnnotation = IdentityAnnotation(target.toNamed, value) + def transformClass: Class[IdentityTransform] = classOf[IdentityTransform] } -object identify { +object identify { // scalastyle:ignore object.name def apply(component: InstanceId, value: String): Unit = { val anno = IdentityChiselAnnotation(component, value) annotate(anno) @@ -35,8 +35,8 @@ object identify { } class IdentityTransform extends Transform { - def inputForm = LowForm - def outputForm = LowForm + def inputForm: CircuitForm = LowForm + def outputForm: CircuitForm = LowForm def execute(state: CircuitState): CircuitState = { val annosx = state.annotations.map { diff --git a/src/test/scala/chiselTests/AnnotationNoDedup.scala b/src/test/scala/chiselTests/AnnotationNoDedup.scala index d93da31f..0f195fdf 100644 --- a/src/test/scala/chiselTests/AnnotationNoDedup.scala +++ b/src/test/scala/chiselTests/AnnotationNoDedup.scala @@ -46,6 +46,7 @@ class UsesMuchUsedModule(addAnnos: Boolean) extends Module { } class AnnotationNoDedup extends FreeSpec with Matchers { + // scalastyle:off line.size.limit "Firrtl provides transform that reduces identical modules to a single instance" - { "Annotations can be added which will prevent this deduplication for specific modules instances" in { Driver.execute(Array("-X", "low", "--target-dir", "test_run_dir"), () => new UsesMuchUsedModule(addAnnos = true)) match { @@ -74,4 +75,5 @@ class AnnotationNoDedup extends FreeSpec with Matchers { } } } + // scalastyle:on line.size.limit } diff --git a/src/test/scala/chiselTests/AutoClonetypeSpec.scala b/src/test/scala/chiselTests/AutoClonetypeSpec.scala index cf88fd2e..75fb46b8 100644 --- a/src/test/scala/chiselTests/AutoClonetypeSpec.scala +++ b/src/test/scala/chiselTests/AutoClonetypeSpec.scala @@ -25,7 +25,7 @@ class BaseBundleVal(val i: Int) extends Bundle { class SubBundle(i: Int, val i2: Int) extends BaseBundleVal(i) { val inner2 = UInt(i2.W) } -class SubBundleInvalid(i: Int, val i2: Int) extends BaseBundleVal(i+1) { +class SubBundleInvalid(i: Int, val i2: Int) extends BaseBundleVal(i + 1) { val inner2 = UInt(i2.W) } @@ -164,7 +164,7 @@ class AutoClonetypeSpec extends ChiselFlatSpec { "3.0 null compatibility" should "not need clonetype" in { elaborate { new Module { class InnerClassThing { - def createBundle = new Bundle { + def createBundle: Bundle = new Bundle { val a = Output(UInt(8.W)) } } diff --git a/src/test/scala/chiselTests/AutoNestedCloneSpec.scala b/src/test/scala/chiselTests/AutoNestedCloneSpec.scala index fc8eb73b..7533b873 100644 --- a/src/test/scala/chiselTests/AutoNestedCloneSpec.scala +++ b/src/test/scala/chiselTests/AutoNestedCloneSpec.scala @@ -21,7 +21,7 @@ class AutoNestedCloneSpec extends ChiselFlatSpec with Matchers { class InnerIOType extends Bundle { val in = Input(UInt(w.W)) } - def getIO = new InnerIOType + def getIO: InnerIOType = new InnerIOType } val io = IO(new Bundle {}) val myWire = Wire((new Middle(w)).getIO) @@ -107,7 +107,7 @@ class AutoNestedCloneSpec extends ChiselFlatSpec with Matchers { intercept[ChiselException] { elaborate { class Outer(val w: Int) extends Module { class Middle(val w: Int) { - def getIO = new Bundle { + def getIO: Bundle = new Bundle { val in = Input(UInt(w.W)) } } diff --git a/src/test/scala/chiselTests/BetterNamingTests.scala b/src/test/scala/chiselTests/BetterNamingTests.scala index d8fc70ac..1b91da3c 100644 --- a/src/test/scala/chiselTests/BetterNamingTests.scala +++ b/src/test/scala/chiselTests/BetterNamingTests.scala @@ -1,3 +1,5 @@ +// See LICENSE for license details. + package chiselTests import collection.mutable diff --git a/src/test/scala/chiselTests/BoringUtilsSpec.scala b/src/test/scala/chiselTests/BoringUtilsSpec.scala index 06840577..80bea3a0 100644 --- a/src/test/scala/chiselTests/BoringUtilsSpec.scala +++ b/src/test/scala/chiselTests/BoringUtilsSpec.scala @@ -11,7 +11,7 @@ import chisel3.experimental.{BaseModule, ChiselAnnotation, MultiIOModule, RawMod import chisel3.util.experimental.BoringUtils import firrtl.{CircuitForm, CircuitState, ChirrtlForm, Transform} -import firrtl.annotations.NoTargetAnnotation +import firrtl.annotations.{Annotation, NoTargetAnnotation} import firrtl.transforms.{DontTouchAnnotation, NoDedupAnnotation} import firrtl.passes.wiring.WiringException @@ -51,7 +51,9 @@ class BoringUtilsSpec extends ChiselFlatSpec with ChiselRunners { trait WireX { this: BaseModule => val x = Wire(UInt(4.W)) - chisel3.experimental.annotate(new ChiselAnnotation{ def toFirrtl = DontTouchAnnotation(x.toNamed) }) + chisel3.experimental.annotate(new ChiselAnnotation { + def toFirrtl: Annotation = DontTouchAnnotation(x.toNamed) + }) } class Source extends RawModule with WireX { @@ -77,8 +79,9 @@ class BoringUtilsSpec extends ChiselFlatSpec with ChiselRunners { sinks.zip(Seq(0, 1, 1, 2, 2, 2)).map{ case (a, b) => chisel3.assert(a.out === b.U) } } - /** This is testing a complicated wiring pattern and exercising the necessity of disabling deduplication for sources and - * sinks. Without disabling deduplication, this test will fail. + /** This is testing a complicated wiring pattern and exercising + * the necessity of disabling deduplication for sources and sinks. + * Without disabling deduplication, this test will fail. */ class TopTester extends ShouldntAssertTester { val dut = Module(new Top(4)) @@ -90,14 +93,14 @@ class BoringUtilsSpec extends ChiselFlatSpec with ChiselRunners { case object FooAnnotation extends NoTargetAnnotation chisel3.experimental.annotate( new ChiselAnnotation with RunFirrtlTransform { - def toFirrtl = FooAnnotation - def transformClass = classOf[StripNoDedupAnnotation] } ) + def toFirrtl: Annotation = FooAnnotation + def transformClass: Class[_ <: Transform] = classOf[StripNoDedupAnnotation] } ) } behavior of "BoringUtils.bore" it should "connect across modules using BoringUtils.bore" in { - runTester(new TopTester) should be (true) + runTester(new TopTester) should be (true) } it should "throw an exception if NoDedupAnnotations are removed" in { diff --git a/src/test/scala/chiselTests/BundleLiteralSpec.scala b/src/test/scala/chiselTests/BundleLiteralSpec.scala index 7d28660b..9db602ee 100644 --- a/src/test/scala/chiselTests/BundleLiteralSpec.scala +++ b/src/test/scala/chiselTests/BundleLiteralSpec.scala @@ -18,7 +18,7 @@ class BundleLiteralSpec extends ChiselFlatSpec { import chisel3.core.BundleLitBinding import chisel3.internal.firrtl.{ULit, Width} // Full bundle literal constructor - def Lit(aVal: UInt, bVal: Bool): MyBundle = { + def Lit(aVal: UInt, bVal: Bool): MyBundle = { // scalastyle:ignore method.name val clone = cloneType clone.selfBind(BundleLitBinding(Map( clone.a -> litArgOfBits(aVal), @@ -27,7 +27,7 @@ class BundleLiteralSpec extends ChiselFlatSpec { clone } // Partial bundle literal constructor - def Lit(aVal: UInt): MyBundle = { + def Lit(aVal: UInt): MyBundle = { // scalastyle:ignore method.name val clone = cloneType clone.selfBind(BundleLitBinding(Map( clone.a -> litArgOfBits(aVal) diff --git a/src/test/scala/chiselTests/BundleSpec.scala b/src/test/scala/chiselTests/BundleSpec.scala index 502134b4..4fc7d7d0 100644 --- a/src/test/scala/chiselTests/BundleSpec.scala +++ b/src/test/scala/chiselTests/BundleSpec.scala @@ -10,25 +10,25 @@ trait BundleSpecUtils { class BundleFooBar extends Bundle { val foo = UInt(16.W) val bar = UInt(16.W) - override def cloneType = (new BundleFooBar).asInstanceOf[this.type] + override def cloneType: this.type = (new BundleFooBar).asInstanceOf[this.type] } class BundleBarFoo extends Bundle { val bar = UInt(16.W) val foo = UInt(16.W) - override def cloneType = (new BundleBarFoo).asInstanceOf[this.type] + override def cloneType: this.type = (new BundleBarFoo).asInstanceOf[this.type] } class BundleFoo extends Bundle { val foo = UInt(16.W) - override def cloneType = (new BundleFoo).asInstanceOf[this.type] + override def cloneType: this.type = (new BundleFoo).asInstanceOf[this.type] } class BundleBar extends Bundle { val bar = UInt(16.W) - override def cloneType = (new BundleBar).asInstanceOf[this.type] + override def cloneType: this.type = (new BundleBar).asInstanceOf[this.type] } class BadSeqBundle extends Bundle { val bar = Seq(UInt(16.W), UInt(8.W), UInt(4.W)) - override def cloneType = (new BadSeqBundle).asInstanceOf[this.type] + override def cloneType: this.type = (new BadSeqBundle).asInstanceOf[this.type] } class MyModule(output: Bundle, input: Bundle) extends Module { diff --git a/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala b/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala index 95dc87c1..02b35734 100644 --- a/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala +++ b/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala @@ -13,11 +13,11 @@ object CompatibilityComponents { val a = UInt(width = 32) val b = UInt(width = 32).flip - override def cloneType = (new ChiselBundle).asInstanceOf[this.type] + override def cloneType: this.type = (new ChiselBundle).asInstanceOf[this.type] } class ChiselRecord extends Record { val elements = ListMap("a" -> UInt(width = 32), "b" -> UInt(width = 32).flip) - override def cloneType = (new ChiselRecord).asInstanceOf[this.type] + override def cloneType: this.type = (new ChiselRecord).asInstanceOf[this.type] } abstract class ChiselDriverModule(_io: => Record) extends Module { @@ -49,12 +49,12 @@ object Chisel3Components { val a = Output(UInt(32.W)) val b = Input(UInt(32.W)) - override def cloneType = (new Chisel3Bundle).asInstanceOf[this.type] + override def cloneType: this.type = (new Chisel3Bundle).asInstanceOf[this.type] } class Chisel3Record extends Record { val elements = ListMap("a" -> Output(UInt(32.W)), "b" -> Input(UInt(32.W))) - override def cloneType = (new Chisel3Record).asInstanceOf[this.type] + override def cloneType: this.type = (new Chisel3Record).asInstanceOf[this.type] } abstract class Chisel3DriverModule(_io: => Record) extends Module { diff --git a/src/test/scala/chiselTests/CompatibilitySpec.scala b/src/test/scala/chiselTests/CompatibilitySpec.scala index 339f2af1..57cb5ec3 100644 --- a/src/test/scala/chiselTests/CompatibilitySpec.scala +++ b/src/test/scala/chiselTests/CompatibilitySpec.scala @@ -47,7 +47,7 @@ class CompatibiltySpec extends ChiselFlatSpec with GeneratorDrivenPropertyChecks val value: Int = Gen.choose(2, 2048).sample.get log2Up(value) shouldBe (1 max BigInt(value - 1).bitLength) log2Ceil(value) shouldBe (BigInt(value - 1).bitLength) - log2Down(value) shouldBe ((1 max BigInt(value - 1).bitLength) - (if (value > 0 && ((value & (value - 1)) == 0)) 0 else 1)) + log2Down(value) shouldBe ((1 max BigInt(value - 1).bitLength) - (if (value > 0 && ((value & (value - 1)) == 0)) 0 else 1)) // scalastyle:ignore line.size.limit log2Floor(value) shouldBe (BigInt(value - 1).bitLength - (if (value > 0 && ((value & (value - 1)) == 0)) 0 else 1)) isPow2(BigInt(1) << value) shouldBe true isPow2((BigInt(1) << value) - 1) shouldBe false @@ -189,6 +189,7 @@ class CompatibiltySpec extends ChiselFlatSpec with GeneratorDrivenPropertyChecks override def cloneType: this.type = (new BigBundle).asInstanceOf[this.type] } + // scalastyle:off line.size.limit "A Module with missing bundle fields when compiled with the Chisel compatibility package" should "not throw an exception" in { class ConnectFieldMismatchModule extends Module { @@ -335,5 +336,5 @@ class CompatibiltySpec extends ChiselFlatSpec with GeneratorDrivenPropertyChecks Chisel.assert(io.bar.dir == INPUT) }) } - + // scalastyle:on line.size.limit } diff --git a/src/test/scala/chiselTests/CompileOptionsTest.scala b/src/test/scala/chiselTests/CompileOptionsTest.scala index 299ce4dd..4f647442 100644 --- a/src/test/scala/chiselTests/CompileOptionsTest.scala +++ b/src/test/scala/chiselTests/CompileOptionsTest.scala @@ -21,6 +21,7 @@ class CompileOptionsSpec extends ChiselFlatSpec { override def cloneType: this.type = (new BigBundle).asInstanceOf[this.type] } + // scalastyle:off line.size.limit "A Module with missing bundle fields when compiled with implicit Strict.CompileOption " should "throw an exception" in { a [ChiselException] should be thrownBy { import chisel3.core.ExplicitCompileOptions.Strict @@ -184,4 +185,5 @@ class CompileOptionsSpec extends ChiselFlatSpec { } elaborate { new DirectionLessConnectionModule() } } + // scalastyle:on line.size.limit } diff --git a/src/test/scala/chiselTests/DataPrint.scala b/src/test/scala/chiselTests/DataPrint.scala index 662d8e1a..bec722f3 100644 --- a/src/test/scala/chiselTests/DataPrint.scala +++ b/src/test/scala/chiselTests/DataPrint.scala @@ -22,7 +22,7 @@ class DataPrintSpec extends ChiselFlatSpec with Matchers { import chisel3.core.BundleLitBinding import chisel3.internal.firrtl.{ULit, Width} // Full bundle literal constructor - def Lit(aVal: UInt, bVal: Bool): BundleTest = { + def Lit(aVal: UInt, bVal: Bool): BundleTest = { // scalastyle:ignore method.name val clone = cloneType clone.selfBind(BundleLitBinding(Map( clone.a -> litArgOfBits(aVal), diff --git a/src/test/scala/chiselTests/EnableShiftRegister.scala b/src/test/scala/chiselTests/EnableShiftRegister.scala index 94e54760..db569233 100644 --- a/src/test/scala/chiselTests/EnableShiftRegister.scala +++ b/src/test/scala/chiselTests/EnableShiftRegister.scala @@ -23,6 +23,7 @@ class EnableShiftRegister extends Module { io.out := r3 } +// scalastyle:off regex /* class EnableShiftRegisterTester(c: EnableShiftRegister) extends Tester(c) { val reg = Array.fill(4){ 0 } @@ -42,6 +43,7 @@ class EnableShiftRegisterTester(c: EnableShiftRegister) extends Tester(c) { } } */ +// scalastyle:on regex class EnableShiftRegisterSpec extends ChiselPropSpec { diff --git a/src/test/scala/chiselTests/FixedPointSpec.scala b/src/test/scala/chiselTests/FixedPointSpec.scala index 137ffc76..a928f08e 100644 --- a/src/test/scala/chiselTests/FixedPointSpec.scala +++ b/src/test/scala/chiselTests/FixedPointSpec.scala @@ -84,12 +84,12 @@ class FixedPointMuxTester extends BasicTester { val unknownWidthLowPrecision = 6.0.F(0.BP) val unknownFixed = Wire(FixedPoint()) unknownFixed := smallWidthHighPrecision - + assert(Mux(true.B, largeWidthLowPrecision, smallWidthHighPrecision) === 6.0.F(0.BP)) assert(Mux(false.B, largeWidthLowPrecision, smallWidthHighPrecision) === 0.25.F(2.BP)) assert(Mux(false.B, largeWidthLowPrecision, unknownFixed) === 0.25.F(2.BP)) assert(Mux(true.B, unknownWidthLowPrecision, smallWidthHighPrecision) === 6.0.F(0.BP)) - + stop() } diff --git a/src/test/scala/chiselTests/InvalidateAPISpec.scala b/src/test/scala/chiselTests/InvalidateAPISpec.scala index c0a643cc..8dfb078b 100644 --- a/src/test/scala/chiselTests/InvalidateAPISpec.scala +++ b/src/test/scala/chiselTests/InvalidateAPISpec.scala @@ -21,6 +21,7 @@ class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompila val out = Output(Bool()) } + // scalastyle:off line.size.limit property("an output connected to DontCare should emit a Firrtl \"is invalid\" with Strict CompileOptions") { import chisel3.core.ExplicitCompileOptions.Strict class ModuleWithDontCare extends Module { @@ -207,4 +208,5 @@ class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompila val firrtlOutput = myGenerateFirrtl(new ModuleWithoutDontCare) firrtlOutput should include("is invalid") } + // scalastyle:on line.size.limit } diff --git a/src/test/scala/chiselTests/LiteralExtractorSpec.scala b/src/test/scala/chiselTests/LiteralExtractorSpec.scala index 2879f2d9..25979488 100644 --- a/src/test/scala/chiselTests/LiteralExtractorSpec.scala +++ b/src/test/scala/chiselTests/LiteralExtractorSpec.scala @@ -63,7 +63,7 @@ class LiteralExtractorSpec extends ChiselFlatSpec { val y = FixedPoint(8.W, 4.BP) import chisel3.core.BundleLitBinding - def Lit(aVal: SInt, bVal: FixedPoint): InsideBundle = { + def Lit(aVal: SInt, bVal: FixedPoint): InsideBundle = { // scalastyle:ignore method.name val clone = cloneType clone.selfBind(BundleLitBinding(Map( clone.x -> litArgOfBits(aVal), @@ -78,7 +78,7 @@ class LiteralExtractorSpec extends ChiselFlatSpec { // the following errors with "assertion failed" - println(outsideLiteral === insideLiteral) + println(outsideLiteral === insideLiteral) // scalastyle:ignore regex // chisel3.core.assert(outsideLiteral === insideLiteral) // the following lines of code error @@ -107,7 +107,7 @@ class LiteralExtractorSpec extends ChiselFlatSpec { // the future. import chisel3.core.BundleLitBinding import chisel3.internal.firrtl.{ULit, Width} - def Lit(aVal: UInt, bVal: Bool): MyBundle = { + def Lit(aVal: UInt, bVal: Bool): MyBundle = { // scalastyle:ignore method.name val clone = cloneType clone.selfBind(BundleLitBinding(Map( clone.a -> litArgOfBits(aVal), diff --git a/src/test/scala/chiselTests/MissingCloneBindingExceptionSpec.scala b/src/test/scala/chiselTests/MissingCloneBindingExceptionSpec.scala index b83557cc..c2c69bbf 100644 --- a/src/test/scala/chiselTests/MissingCloneBindingExceptionSpec.scala +++ b/src/test/scala/chiselTests/MissingCloneBindingExceptionSpec.scala @@ -13,7 +13,7 @@ class MissingCloneBindingExceptionSpec extends ChiselFlatSpec with Matchers { class TestIO(w: Int) extends Bundle { val a = Input(Vec(4, UInt(w.W))) } - + val io = IO(new TestIO(32)) } @@ -36,7 +36,7 @@ class MissingCloneBindingExceptionSpec extends ChiselFlatSpec with Matchers { class TestIO(w: Int) extends Bundle { val a = Vec(4, UInt(width = w)).asInput } - + val io = IO(new TestIO(32)) } diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala index a973412e..46e60064 100644 --- a/src/test/scala/chiselTests/Module.scala +++ b/src/test/scala/chiselTests/Module.scala @@ -70,7 +70,7 @@ class ModuleWrapper(gen: => Module) extends Module { class NullModuleWrapper extends Module { val io = IO(new Bundle{}) override lazy val desiredName = s"${child.desiredName}Wrapper" - println(s"My name is ${name}") + println(s"My name is ${name}") // scalastyle:ignore regex val child = Module(new ModuleWire) } diff --git a/src/test/scala/chiselTests/MultiAssign.scala b/src/test/scala/chiselTests/MultiAssign.scala index 1e1d3f70..745e25de 100644 --- a/src/test/scala/chiselTests/MultiAssign.scala +++ b/src/test/scala/chiselTests/MultiAssign.scala @@ -40,7 +40,7 @@ class IllegalAssignSpec extends ChiselFlatSpec { }} } } - + "Reassignments to ops" should "be disallowed" in { intercept[chisel3.internal.ChiselException] { elaborate{ new BasicTester { @@ -48,7 +48,7 @@ class IllegalAssignSpec extends ChiselFlatSpec { }} } } - + "Reassignments to bit slices" should "be disallowed" in { intercept[chisel3.internal.ChiselException] { elaborate{ new BasicTester { @@ -56,7 +56,7 @@ class IllegalAssignSpec extends ChiselFlatSpec { }} } } - + "Bulk-connecting two read-only nodes" should "be disallowed" in { intercept[chisel3.internal.ChiselException] { elaborate{ new BasicTester { diff --git a/src/test/scala/chiselTests/MultiIOModule.scala b/src/test/scala/chiselTests/MultiIOModule.scala index 07e09041..7978970a 100644 --- a/src/test/scala/chiselTests/MultiIOModule.scala +++ b/src/test/scala/chiselTests/MultiIOModule.scala @@ -34,7 +34,7 @@ trait MultiIOTrait extends MultiIOModule { // Composition of the two above traits, example of IO composition directly using multiple top-level // IOs rather than indirectly by constraining the type of the single .io field. -class ComposedMultiIOModule extends MultiIOModule +class ComposedMultiIOModule extends MultiIOModule with LiteralOutputTrait with MultiIOTrait { val topModuleIO = IO(Input(UInt(32.W))) myTraitIO := topModuleIO diff --git a/src/test/scala/chiselTests/MuxSpec.scala b/src/test/scala/chiselTests/MuxSpec.scala index d06c00af..0ead960a 100644 --- a/src/test/scala/chiselTests/MuxSpec.scala +++ b/src/test/scala/chiselTests/MuxSpec.scala @@ -1,3 +1,5 @@ +// See LICENSE for license details. + package chiselTests import chisel3._ @@ -22,4 +24,4 @@ class MuxSpec extends ChiselFlatSpec { "Mux" should "pass basic checks" in { assertTesterPasses { new MuxTester } } -}
\ No newline at end of file +} diff --git a/src/test/scala/chiselTests/NamingAnnotationTest.scala b/src/test/scala/chiselTests/NamingAnnotationTest.scala index ec0874fc..9fdf0695 100644 --- a/src/test/scala/chiselTests/NamingAnnotationTest.scala +++ b/src/test/scala/chiselTests/NamingAnnotationTest.scala @@ -54,7 +54,7 @@ trait NamedModuleTester extends MultiIOModule { @chiselName class NamedModule extends NamedModuleTester { @chiselName - def FunctionMockupInner(): UInt = { + def FunctionMockupInner(): UInt = { // scalastyle:ignore method.name val my2A = 1.U val my2B = expectName(my2A +& 2.U, "test_myNested_my2B") val my2C = my2B +& 3.U // should get named at enclosing scope @@ -62,7 +62,7 @@ class NamedModule extends NamedModuleTester { } @chiselName - def FunctionMockup(): UInt = { + def FunctionMockup(): UInt = { // scalastyle:ignore method.name val myNested = expectName(FunctionMockupInner(), "test_myNested") val myA = expectName(1.U + myNested, "test_myA") val myB = expectName(myA +& 2.U, "test_myB") @@ -76,14 +76,14 @@ class NamedModule extends NamedModuleTester { } // chiselName "implicitly" applied - def ImplicitlyNamed(): UInt = { + def ImplicitlyNamed(): UInt = { // scalastyle:ignore method.name val implicitA = expectName(1.U + 2.U, "test3_implicitA") val implicitB = expectName(implicitA + 3.U, "test3_implicitB") implicitB + 2.U // named at enclosing scope } // Ensure this applies a partial name if there is no return value - def NoReturnFunction() { + def NoReturnFunction() { // scalastyle:ignore method.name val noreturn = expectName(1.U + 2.U, "noreturn") } @@ -132,7 +132,7 @@ class NameCollisionModule extends NamedModuleTester { */ class NonNamedModule extends NamedModuleTester { @chiselName - def NamedFunction(): UInt = { + def NamedFunction(): UInt = { // scalastyle:ignore method.name val myVal = 1.U + 2.U myVal } @@ -145,12 +145,12 @@ class NonNamedModule extends NamedModuleTester { */ object NonNamedHelper { @chiselName - def NamedFunction(): UInt = { + def NamedFunction(): UInt = { // scalastyle:ignore method.name val myVal = 1.U + 2.U myVal } - def NonNamedFunction() : UInt = { + def NonNamedFunction() : UInt = { // scalastyle:ignore method.name val myVal = NamedFunction() myVal } diff --git a/src/test/scala/chiselTests/PrintableSpec.scala b/src/test/scala/chiselTests/PrintableSpec.scala index 6ae38a24..7ba4bf5d 100644 --- a/src/test/scala/chiselTests/PrintableSpec.scala +++ b/src/test/scala/chiselTests/PrintableSpec.scala @@ -1,3 +1,5 @@ +// See LICENSE for license details. + package chiselTests import org.scalatest.{FlatSpec, Matchers} @@ -105,10 +107,10 @@ class PrintableSpec extends FlatSpec with Matchers { } class MyBundle extends Bundle { val foo = UInt(32.W) - override def cloneType = (new MyBundle).asInstanceOf[this.type] + override def cloneType: this.type = (new MyBundle).asInstanceOf[this.type] } class MyModule extends BasicTester { - override def desiredName = "MyModule" + override def desiredName: String = "MyModule" val myWire = Wire(new MyBundle) val myInst = Module(new MySubModule) printf(p"${Name(myWire.foo)}") @@ -116,7 +118,7 @@ class PrintableSpec extends FlatSpec with Matchers { printf(p"${FullName(myInst.io.fizz)}") } val firrtl = Driver.emit(() => new MyModule) - println(firrtl) + println(firrtl) // scalastyle:ignore regex getPrintfs(firrtl) match { case Seq(Printf("foo", Seq()), Printf("myWire.foo", Seq()), diff --git a/src/test/scala/chiselTests/RecordSpec.scala b/src/test/scala/chiselTests/RecordSpec.scala index 2eb7cfc8..bf6b92eb 100644 --- a/src/test/scala/chiselTests/RecordSpec.scala +++ b/src/test/scala/chiselTests/RecordSpec.scala @@ -18,7 +18,7 @@ final class CustomBundle(elts: (String, Data)*) extends Record { field -> elt }: _*) def apply(elt: String): Data = elements(elt) - override def cloneType = { + override def cloneType: this.type = { val cloned = elts.map { case (n, d) => n -> DataMirror.internal.chiselTypeClone(d) } (new CustomBundle(cloned: _*)).asInstanceOf[this.type] } @@ -28,11 +28,11 @@ trait RecordSpecUtils { class MyBundle extends Bundle { val foo = UInt(32.W) val bar = UInt(32.W) - override def cloneType = (new MyBundle).asInstanceOf[this.type] + override def cloneType: this.type = (new MyBundle).asInstanceOf[this.type] } // Useful for constructing types from CustomBundle // This is a def because each call to this needs to return a new instance - def fooBarType = new CustomBundle("foo" -> UInt(32.W), "bar" -> UInt(32.W)) + def fooBarType: CustomBundle = new CustomBundle("foo" -> UInt(32.W), "bar" -> UInt(32.W)) class MyModule(output: => Record, input: => Record) extends Module { val io = IO(new Bundle { diff --git a/src/test/scala/chiselTests/Risc.scala b/src/test/scala/chiselTests/Risc.scala index 07efb7dc..21b638e5 100644 --- a/src/test/scala/chiselTests/Risc.scala +++ b/src/test/scala/chiselTests/Risc.scala @@ -54,6 +54,7 @@ class Risc extends Module { } } +// scalastyle:off regex /* class RiscTester(c: Risc) extends Tester(c) { def wr(addr: BigInt, data: BigInt) = { @@ -111,6 +112,7 @@ class RiscTester(c: Risc) extends Tester(c) { expect(c.io.out, 4) } */ +// scalastyle:on regex class RiscSpec extends ChiselPropSpec { diff --git a/src/test/scala/chiselTests/Stack.scala b/src/test/scala/chiselTests/Stack.scala index 3cdb68eb..9f17c741 100644 --- a/src/test/scala/chiselTests/Stack.scala +++ b/src/test/scala/chiselTests/Stack.scala @@ -17,7 +17,7 @@ class ChiselStack(val depth: Int) extends Module { }) val stack_mem = Mem(depth, UInt(32.W)) - val sp = RegInit(0.U(log2Ceil(depth+1).W)) + val sp = RegInit(0.U(log2Ceil(depth + 1).W)) val out = RegInit(0.U(32.W)) when (io.en) { diff --git a/src/test/scala/chiselTests/StrongEnum.scala b/src/test/scala/chiselTests/StrongEnum.scala index d38aa1e4..f5c3bc2f 100644 --- a/src/test/scala/chiselTests/StrongEnum.scala +++ b/src/test/scala/chiselTests/StrongEnum.scala @@ -7,7 +7,7 @@ import chisel3.experimental.ChiselEnum import chisel3.internal.firrtl.UnknownWidth import chisel3.util._ import chisel3.testers.BasicTester -import org.scalatest.{FreeSpec, Matchers} +import org.scalatest.{Assertion, FreeSpec, Matchers} object EnumExample extends ChiselEnum { val e0, e1, e2 = Value @@ -252,7 +252,7 @@ class StrongEnumFSMTester extends BasicTester { // Inputs and expected results val inputs: Vec[Bool] = VecInit(false.B, true.B, false.B, true.B, true.B, true.B, false.B, true.B, true.B, false.B) - val expected: Vec[Bool] = VecInit(false.B, false.B, false.B, false.B, false.B, true.B, true.B, false.B, false.B, true.B) + val expected: Vec[Bool] = VecInit(false.B, false.B, false.B, false.B, false.B, true.B, true.B, false.B, false.B, true.B) // scalastyle:ignore line.size.limit val expected_state = VecInit(sNone, sNone, sOne1, sNone, sOne1, sTwo1s, sTwo1s, sNone, sOne1, sTwo1s) val cntr = Counter(inputs.length) @@ -331,7 +331,7 @@ class StrongEnumSpec extends ChiselFlatSpec { elaborate(new CastFromNonLitWidth) } - for (w <- (EnumExample.getWidth+1) to (EnumExample.getWidth+100)) { + for (w <- (EnumExample.getWidth + 1) to (EnumExample.getWidth + 100)) { a [ChiselException] should be thrownBy { elaborate(new CastFromNonLitWidth(Some(w))) } @@ -361,7 +361,7 @@ class StrongEnumSpec extends ChiselFlatSpec { } it should "maintain Scala-level type-safety" in { - def foo(e: EnumExample.Type) = {} + def foo(e: EnumExample.Type): Unit = {} "foo(EnumExample.e1); foo(EnumExample.e1.next)" should compile "foo(OtherEnum.otherEnum)" shouldNot compile @@ -378,7 +378,8 @@ class StrongEnumAnnotationSpec extends ChiselFlatSpec { ignore should "Test that strong enums annotate themselves appropriately" in { - def test() = { + // scalastyle:off regex + def test(): Assertion = {// scalastyle:ignore cyclomatic.complexity Driver.execute(Array("--target-dir", "test_run_dir"), () => new StrongEnumFSM) match { case ChiselExecutionSuccess(Some(circuit), emitted, _) => val annos = circuit.annotations.map(_.toFirrtl) @@ -421,6 +422,7 @@ class StrongEnumAnnotationSpec extends ChiselFlatSpec { case _ => assert(false) } + // scalastyle:on regex } // We run this test twice, to test for an older bug where only the first circuit would be annotated diff --git a/src/test/scala/chiselTests/Util.scala b/src/test/scala/chiselTests/Util.scala index 80e37285..82ae7072 100644 --- a/src/test/scala/chiselTests/Util.scala +++ b/src/test/scala/chiselTests/Util.scala @@ -1,3 +1,5 @@ +// See LICENSE for license details. + // Useful utilities for tests package chiselTests diff --git a/src/test/scala/chiselTests/WidthSpec.scala b/src/test/scala/chiselTests/WidthSpec.scala index 4fcebb32..0e76fdca 100644 --- a/src/test/scala/chiselTests/WidthSpec.scala +++ b/src/test/scala/chiselTests/WidthSpec.scala @@ -70,11 +70,11 @@ abstract class WireRegWidthSpecImpl extends ChiselFlatSpec { } class WireWidthSpec extends WireRegWidthSpecImpl { - def name = "Wire" + def name: String = "Wire" def builder[T <: Data](x: T): T = Wire(x) } class RegWidthSpec extends WireRegWidthSpecImpl { - def name = "Reg" + def name: String = "Reg" def builder[T <: Data](x: T): T = Reg(x) } @@ -175,13 +175,13 @@ abstract class WireDefaultRegInitSpecImpl extends ChiselFlatSpec { } class WireDefaultWidthSpec extends WireDefaultRegInitSpecImpl { - def name = "WireDefault" + def name: String = "WireDefault" def builder1[T <: Data](x: T): T = WireDefault(x) def builder2[T <: Data](x: T, y: T): T = WireDefault(x, y) } class RegInitWidthSpec extends WireDefaultRegInitSpecImpl { - def name = "RegInit" + def name: String = "RegInit" def builder1[T <: Data](x: T): T = RegInit(x) def builder2[T <: Data](x: T, y: T): T = RegInit(x, y) } diff --git a/src/test/scala/cookbook/FSM.scala b/src/test/scala/cookbook/FSM.scala index 170d110f..f33bfee4 100644 --- a/src/test/scala/cookbook/FSM.scala +++ b/src/test/scala/cookbook/FSM.scala @@ -53,7 +53,7 @@ class DetectTwoOnesTester extends CookbookTester(10) { // Inputs and expected results val inputs: Vec[Bool] = VecInit(false.B, true.B, false.B, true.B, true.B, true.B, false.B, true.B, true.B, false.B) - val expected: Vec[Bool] = VecInit(false.B, false.B, false.B, false.B, false.B, true.B, true.B, false.B, false.B, true.B) + val expected: Vec[Bool] = VecInit(false.B, false.B, false.B, false.B, false.B, true.B, true.B, false.B, false.B, true.B) // scalastyle:ignore line.size.limit dut.io.in := inputs(cycle) assert(dut.io.out === expected(cycle)) |