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-rw-r--r--src/main/scala/chisel3/internal/firrtl/Emitter.scala15
1 files changed, 13 insertions, 2 deletions
diff --git a/src/main/scala/chisel3/internal/firrtl/Emitter.scala b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
index 53329908..a94558ce 100644
--- a/src/main/scala/chisel3/internal/firrtl/Emitter.scala
+++ b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
@@ -1,12 +1,23 @@
// SPDX-License-Identifier: Apache-2.0
package chisel3.internal.firrtl
-import firrtl.{ir => fir}
+
+import scala.collection.immutable.LazyList // Needed for 2.12 alias
+import firrtl.ir.Serializer
private[chisel3] object Emitter {
def emit(circuit: Circuit): String = {
val fcircuit = Converter.convertLazily(circuit)
- fir.Serializer.serialize(fcircuit)
+ Serializer.serialize(fcircuit)
+ }
+
+ def emitLazily(circuit: Circuit): Iterable[String] = {
+ val result = LazyList(s"circuit ${circuit.name} :\n")
+ val modules = circuit.components.view.map(Converter.convert)
+ val moduleStrings = modules.flatMap { m =>
+ Array(Serializer.serialize(m, 1), "\n\n")
+ }
+ result ++ moduleStrings
}
}