diff options
| author | Jack Koenig | 2021-08-20 12:00:08 -0700 |
|---|---|---|
| committer | Jack Koenig | 2021-08-23 17:13:48 -0700 |
| commit | d9c30ea0fdd90f3e47cae161f4a7224a861a6bf0 (patch) | |
| tree | 40413b1898ed2e6c8d6bfdb1b1c02dd4d628c313 /src/main/scala/chisel3/internal | |
| parent | 73bd4ee6b9b510725b692c33e075362a19512d2c (diff) | |
Emit .fir lazily, overcomes JVM 2 GiB String limit
Diffstat (limited to 'src/main/scala/chisel3/internal')
| -rw-r--r-- | src/main/scala/chisel3/internal/firrtl/Emitter.scala | 15 |
1 files changed, 13 insertions, 2 deletions
diff --git a/src/main/scala/chisel3/internal/firrtl/Emitter.scala b/src/main/scala/chisel3/internal/firrtl/Emitter.scala index 53329908..a94558ce 100644 --- a/src/main/scala/chisel3/internal/firrtl/Emitter.scala +++ b/src/main/scala/chisel3/internal/firrtl/Emitter.scala @@ -1,12 +1,23 @@ // SPDX-License-Identifier: Apache-2.0 package chisel3.internal.firrtl -import firrtl.{ir => fir} + +import scala.collection.immutable.LazyList // Needed for 2.12 alias +import firrtl.ir.Serializer private[chisel3] object Emitter { def emit(circuit: Circuit): String = { val fcircuit = Converter.convertLazily(circuit) - fir.Serializer.serialize(fcircuit) + Serializer.serialize(fcircuit) + } + + def emitLazily(circuit: Circuit): Iterable[String] = { + val result = LazyList(s"circuit ${circuit.name} :\n") + val modules = circuit.components.view.map(Converter.convert) + val moduleStrings = modules.flatMap { m => + Array(Serializer.serialize(m, 1), "\n\n") + } + result ++ moduleStrings } } |
