2 files changed, 18 insertions, 4 deletions
diff --git a/src/main/scala/chisel3/internal/firrtl/Emitter.scala b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
index 53329908..a94558ce 100644
--- a/src/main/scala/chisel3/internal/firrtl/Emitter.scala
+++ b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
@@ -1,12 +1,23 @@
 // SPDX-License-Identifier: Apache-2.0
 
 package chisel3.internal.firrtl
-import firrtl.{ir => fir}
+
+import scala.collection.immutable.LazyList // Needed for 2.12 alias
+import firrtl.ir.Serializer
 
 private[chisel3] object Emitter {
   def emit(circuit: Circuit): String = {
     val fcircuit = Converter.convertLazily(circuit)
-    fir.Serializer.serialize(fcircuit)
+    Serializer.serialize(fcircuit)
+  }
+
+  def emitLazily(circuit: Circuit): Iterable[String] = {
+    val result = LazyList(s"circuit ${circuit.name} :\n")
+    val modules = circuit.components.view.map(Converter.convert)
+    val moduleStrings = modules.flatMap { m =>
+      Array(Serializer.serialize(m, 1), "\n\n")
+    }
+    result ++ moduleStrings
   }
 }
 
diff --git a/src/main/scala/chisel3/stage/ChiselAnnotations.scala b/src/main/scala/chisel3/stage/ChiselAnnotations.scala
index b071c60f..6cace05f 100644
--- a/src/main/scala/chisel3/stage/ChiselAnnotations.scala
+++ b/src/main/scala/chisel3/stage/ChiselAnnotations.scala
@@ -133,9 +133,12 @@ case class CircuitSerializationAnnotation(circuit: Circuit, filename: String, fo
 
   protected def suffix: Option[String] = Some(format.extension)
 
-  // TODO Use lazy Iterables so that we don't have to materialize full intermediate data structures
   override def getBytes: Iterable[Byte] = format match {
-    case FirrtlFileFormat => OldEmitter.emit(circuit).getBytes
+    case FirrtlFileFormat =>
+      OldEmitter.emitLazily(circuit)
+                .map(_.getBytes)
+                .flatten
+    // TODO Use lazy Iterables so that we don't have to materialize full intermediate data structures
     case ProtoBufFileFormat =>
       val ostream = new java.io.ByteArrayOutputStream
       val modules = circuit.components.map(m => () => chisel3.internal.firrtl.Converter.convert(m))