Merge branch 'master' of https://github.com/ucb-bar/chisel3

3 files changed, 11 insertions, 3 deletions

diff --git a/src/main/scala/Chisel/Driver.scala b/src/main/scala/Chisel/Driver.scala
index a6f61f69..61b74dcd 100644
--- a/src/main/scala/Chisel/Driver.scala
+++ b/src/main/scala/Chisel/Driver.scala
@@ -114,6 +114,13 @@ object Driver extends BackendCompilationUtilities {
     f
   }
 
-  // FIXME: This is hard coded and should come in from a command-line argument
-  def targetDir(): String = { "vsim/generated-src" }
+  private var target_dir: Option[String] = None
+  def parseArgs(args: Array[String]): Unit = {
+    for (i <- 0 until args.size) {
+      if (args(i) == "--targetDir")
+        target_dir = Some(args(i+1))
+    }
+  }
+
+  def targetDir(): String = { target_dir.get }
 }
diff --git a/src/main/scala/Chisel/Main.scala b/src/main/scala/Chisel/Main.scala
index 750e8712..349f8b18 100644
--- a/src/main/scala/Chisel/Main.scala
+++ b/src/main/scala/Chisel/Main.scala
@@ -11,6 +11,7 @@ import java.io.File
   def run[T <: Module] (args: Array[String], gen: () => T) = {
     def circuit = Driver.elaborate(gen)
     def output_file = new File(Driver.targetDir + "/" + circuit.name + ".fir")
+    Driver.parseArgs(args)
     Driver.dumpFirrtl(circuit, Option(output_file))
   }
 }
diff --git a/src/main/scala/Chisel/internal/firrtl/IR.scala b/src/main/scala/Chisel/internal/firrtl/IR.scala
index 60a38a08..d53807c6 100644
--- a/src/main/scala/Chisel/internal/firrtl/IR.scala
+++ b/src/main/scala/Chisel/internal/firrtl/IR.scala
@@ -57,7 +57,7 @@ abstract class LitArg(val num: BigInt, widthArg: Width) extends Arg {
 
   protected def minWidth: Int
   if (forcedWidth) {
-    require(widthArg.get >= minWidth)
+    require(widthArg.get >= minWidth, s"The literal value ${num} was elaborated with a specificed width of ${widthArg.get} bits, but at least ${minWidth} bits are required.")
   }
 }