diff options
| author | Andrew Waterman | 2016-03-06 20:39:05 -0800 |
|---|---|---|
| committer | Andrew Waterman | 2016-03-06 20:39:05 -0800 |
| commit | 315efd3809454637a6d56958929c7c44943d8812 (patch) | |
| tree | c96e134c311de04466025bd8123b8cad877c219a /src | |
| parent | 2f5819bc5c639e6bed18e901ad0f2bf60f1954a0 (diff) | |
| parent | 4083fcdeaeaeec543fbda48208dde14405f22f8f (diff) | |
Merge pull request #113 from ucb-bar/require-message
Print a better message on constant width failures
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/Chisel/internal/firrtl/IR.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/Chisel/internal/firrtl/IR.scala b/src/main/scala/Chisel/internal/firrtl/IR.scala index 60a38a08..d53807c6 100644 --- a/src/main/scala/Chisel/internal/firrtl/IR.scala +++ b/src/main/scala/Chisel/internal/firrtl/IR.scala @@ -57,7 +57,7 @@ abstract class LitArg(val num: BigInt, widthArg: Width) extends Arg { protected def minWidth: Int if (forcedWidth) { - require(widthArg.get >= minWidth) + require(widthArg.get >= minWidth, s"The literal value ${num} was elaborated with a specificed width of ${widthArg.get} bits, but at least ${minWidth} bits are required.") } } |
