Merge branch 'master' of https://github.com/ucb-bar/chisel3

2 files changed, 97 insertions, 7 deletions

diff --git a/src/main/scala/Chisel/util/Decoupled.scala b/src/main/scala/Chisel/util/Decoupled.scala
index 23a08d52..ba33e6c7 100644
--- a/src/main/scala/Chisel/util/Decoupled.scala
+++ b/src/main/scala/Chisel/util/Decoupled.scala
@@ -22,21 +22,48 @@ object Decoupled {
   def apply[T <: Data](gen: T): DecoupledIO[T] = new DecoupledIO(gen)
 }
 
-/** An I/O bundle for enqueuing data with valid/ready handshaking */
+/** An I/O bundle for enqueuing data with valid/ready handshaking
+  * Initialization must be handled, if necessary, by the parent circuit
+  */
 class EnqIO[T <: Data](gen: T) extends DecoupledIO(gen)
 {
+  /** push dat onto the output bits of this interface to let the consumer know it has happened.
+    * @param dat the values to assign to bits.
+    * @return    dat.
+    */
   def enq(dat: T): T = { valid := Bool(true); bits := dat; dat }
-  valid := Bool(false)
-  for (io <- bits.flatten)
-    io := UInt(0)
+
+  /** Initialize this Bundle.  Valid is set to false, and all bits are set to zero.
+    * NOTE: This method of initialization is still being discussed and could change in the
+    * future.
+    */
+  def init(): Unit = {
+    valid := Bool(false)
+    for (io <- bits.flatten)
+      io := UInt(0)
+  }
   override def cloneType: this.type = { new EnqIO(gen).asInstanceOf[this.type]; }
 }
 
-/** An I/O bundle for dequeuing data with valid/ready handshaking */
+/** An I/O bundle for dequeuing data with valid/ready handshaking.
+  * Initialization must be handled, if necessary, by the parent circuit
+  */
 class DeqIO[T <: Data](gen: T) extends DecoupledIO(gen) with Flipped
 {
-  ready := Bool(false)
+  /** Assert ready on this port and return the associated data bits.
+    * This is typically used when valid has been asserted by the producer side.
+    * @param b ignored
+    * @return the data for this device,
+    */
   def deq(b: Boolean = false): T = { ready := Bool(true); bits }
+
+  /** Initialize this Bundle.
+    * NOTE: This method of initialization is still being discussed and could change in the
+    * future.
+    */
+  def init(): Unit = {
+    ready := Bool(false)
+  }
   override def cloneType: this.type = { new DeqIO(gen).asInstanceOf[this.type]; }
 }
 
@@ -54,7 +81,7 @@ class DecoupledIOC[+T <: Data](gen: T) extends Bundle
 class QueueIO[T <: Data](gen: T, entries: Int) extends Bundle
 {
   /** I/O to enqueue data, is [[Chisel.DecoupledIO]] flipped */
-  val enq   = Decoupled(gen.cloneType).flip
+  val enq   = Decoupled(gen.cloneType).flip()
   /** I/O to enqueue data, is [[Chisel.DecoupledIO]]*/
   val deq   = Decoupled(gen.cloneType)
   /** The current amount of data in the queue */
diff --git a/src/test/scala/chiselTests/VectorPacketIO.scala b/src/test/scala/chiselTests/VectorPacketIO.scala
new file mode 100644
index 00000000..99ec66a6
--- /dev/null
+++ b/src/test/scala/chiselTests/VectorPacketIO.scala
@@ -0,0 +1,63 @@
+// See LICENSE for license details.
+
+package chiselTests
+
+import Chisel._
+import Chisel.testers.BasicTester
+
+/**
+  * This test used to fail when assignment statements were
+  * contained in DeqIO and EnqIO constructors.
+  * The symptom is creation of a firrtl file
+  * with missing declarations, the problem is exposed by
+  * the creation of the val outs in VectorPacketIO
+  *
+  * NOTE: The problem does not exist now because the initialization
+  * code has been removed from DeqIO and EnqIO
+  *
+  * IMPORTANT:  The canonical way to initialize a decoupled inteface is still being debated.
+  */
+class Packet extends Bundle {
+  val header = UInt(width = 1)
+}
+
+/**
+  * The problem occurs with just the ins or the outs
+  * lines also.
+  * The problem does not occur if the Vec is taken out
+  */
+class VectorPacketIO(n: Int) extends Bundle {
+  val ins  = Vec(n, new DeqIO(new Packet()))
+  val outs = Vec(n, new EnqIO(new Packet()))
+}
+
+/**
+  * a module uses the vector based IO bundle
+  * the value of n does not affect the error
+  */
+class BrokenVectorPacketModule extends Module {
+  val n  = 4
+  val io = new VectorPacketIO(n)
+
+  /* the following method of initializing the circuit may change in the future */
+  io.outs.foreach(_.init())
+}
+
+class VectorPacketIOUnitTester extends BasicTester {
+  val device_under_test = Module(new BrokenVectorPacketModule)
+
+  // This counter just makes the test end quicker
+  val c = Counter(1)
+  when(c.inc()) {
+    stop()
+  }
+}
+
+class VectorPacketIOUnitTesterSpec extends ChiselFlatSpec {
+  "a circuit using an io containing a vector of EnqIO wrapped packets" should
+    "compile and run" in {
+    assertTesterPasses {
+      new VectorPacketIOUnitTester
+    }
+  }
+}