Merge branch 'master' of https://github.com/ucb-bar/chisel3

5 files changed, 85 insertions, 16 deletions

diff --git a/.gitignore b/.gitignore
index e59c9b3b..3242c220 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,2 +1,5 @@
 generated/
 /bin/
+.idea
+target/
+*.iml
\ No newline at end of file
diff --git a/build.sbt b/build.sbt
index 664a717e..3cd496bb 100644
--- a/build.sbt
+++ b/build.sbt
@@ -1,22 +1,80 @@
-organization := "edu.berkeley.cs"
+// See LICENSE for license details.
 
-version := "3.0"
+site.settings
 
-name := "Chisel"
+site.includeScaladoc()
 
-scalaVersion := "2.11.6"
+ghpages.settings
 
-libraryDependencies ++= Seq("org.scala-lang" % "scala-reflect" % scalaVersion.value,
-                            "org.scalatest" % "scalatest_2.11" % "2.2.4" % "test",
-                            "org.scalacheck" %% "scalacheck" % "1.12.4" % "test")
+lazy val chiselBuildSettings = Seq (
+  organization := "edu.berkeley.cs",
+  version := "3.0",
+  name := "Chisel3",
+  git.remoteRepo := "git@github.com:ucb-bar/chisel3.git",
 
-site.settings
+  scalaVersion := "2.11.7",
+  publishMavenStyle := true,
+  publishArtifact in Test := false,
+  pomIncludeRepository := { x => false },
+  pomExtra := <url>http://chisel.eecs.berkeley.edu/</url>
+    <licenses>
+      <license>
+        <name>BSD-style</name>
+        <url>http://www.opensource.org/licenses/bsd-license.php</url>
+        <distribution>repo</distribution>
+      </license>
+    </licenses>
+    <scm>
+      <url>https://github.com/ucb-bar/chisel3.git</url>
+      <connection>scm:git:github.com/ucb-bar/chisel3.git</connection>
+    </scm>
+    <developers>
+      <developer>
+        <id>jackbackrack</id>
+        <name>Jonathan Bachrach</name>
+        <url>http://www.eecs.berkeley.edu/~jrb/</url>
+      </developer>
+    </developers>,
 
-site.includeScaladoc()
+  publishTo <<= version { v: String =>
+    val nexus = "https://oss.sonatype.org/"
+    if (v.trim.endsWith("SNAPSHOT")) {
+      Some("snapshots" at nexus + "content/repositories/snapshots")
+    }
+    else {
+      Some("releases" at nexus + "service/local/staging/deploy/maven2")
+    }
+  },
 
-ghpages.settings
+  resolvers ++= Seq(
+    "Sonatype Snapshots" at "http://oss.sonatype.org/content/repositories/snapshots",
+    "Sonatype Releases" at "http://oss.sonatype.org/content/repositories/releases"
+  ),
+
+  /* Bumping "com.novocode" % "junit-interface" % "0.11", causes DelayTest testSeqReadBundle to fail
+   *  in subtly disturbing ways on Linux (but not on Mac):
+   *  - some fields in the generated .h file are re-named,
+   *  - an additional field is added
+   *  - the generated .cpp file has additional differences:
+   *    - different temps in clock_lo
+   *    - missing assignments
+   *    - change of assignment order
+   *    - use of "Tx" vs. "Tx.values"
+   */
+  libraryDependencies += "org.scalatest" %% "scalatest" % "2.2.5" % "test",
+  libraryDependencies += "org.scala-lang" % "scala-reflect" % scalaVersion.value,
+  libraryDependencies += "org.scalacheck" %% "scalacheck" % "1.12.4" % "test",
+
+  // Tests from other projects may still run concurrently.
+  parallelExecution in Test := true,
 
-git.remoteRepo := "git@github.com:ucb-bar/chisel3.git"
+  javacOptions ++= Seq("-target", "1.7")
+  //  Hopefully we get these options back in Chisel3
+  //  scalacOptions in (Compile, doc) <++= (baseDirectory in LocalProject("chisel"), version) map { (bd, v) =>
+  //    Seq("-diagrams", "-diagrams-max-classes", "25", "-sourcepath", bd.getAbsolutePath, "-doc-source-url",
+  //        "https://github.com/ucb-bar/chisel/tree/master/€{FILE_PATH}.scala")
+  //  }
+)
 
-(scalastyleConfig in Test) := baseDirectory.value / "scalastyle-test-config.xml"
-(parallelExecution in Test) := true
+lazy val chisel = (project in file(".")).
+  settings(chiselBuildSettings: _*)
diff --git a/src/main/scala/Chisel/Driver.scala b/src/main/scala/Chisel/Driver.scala
index a6f61f69..61b74dcd 100644
--- a/src/main/scala/Chisel/Driver.scala
+++ b/src/main/scala/Chisel/Driver.scala
@@ -114,6 +114,13 @@ object Driver extends BackendCompilationUtilities {
     f
   }
 
-  // FIXME: This is hard coded and should come in from a command-line argument
-  def targetDir(): String = { "vsim/generated-src" }
+  private var target_dir: Option[String] = None
+  def parseArgs(args: Array[String]): Unit = {
+    for (i <- 0 until args.size) {
+      if (args(i) == "--targetDir")
+        target_dir = Some(args(i+1))
+    }
+  }
+
+  def targetDir(): String = { target_dir.get }
 }
diff --git a/src/main/scala/Chisel/Main.scala b/src/main/scala/Chisel/Main.scala
index 750e8712..349f8b18 100644
--- a/src/main/scala/Chisel/Main.scala
+++ b/src/main/scala/Chisel/Main.scala
@@ -11,6 +11,7 @@ import java.io.File
   def run[T <: Module] (args: Array[String], gen: () => T) = {
     def circuit = Driver.elaborate(gen)
     def output_file = new File(Driver.targetDir + "/" + circuit.name + ".fir")
+    Driver.parseArgs(args)
     Driver.dumpFirrtl(circuit, Option(output_file))
   }
 }
diff --git a/src/main/scala/Chisel/internal/firrtl/IR.scala b/src/main/scala/Chisel/internal/firrtl/IR.scala
index 60a38a08..d53807c6 100644
--- a/src/main/scala/Chisel/internal/firrtl/IR.scala
+++ b/src/main/scala/Chisel/internal/firrtl/IR.scala
@@ -57,7 +57,7 @@ abstract class LitArg(val num: BigInt, widthArg: Width) extends Arg {
 
   protected def minWidth: Int
   if (forcedWidth) {
-    require(widthArg.get >= minWidth)
+    require(widthArg.get >= minWidth, s"The literal value ${num} was elaborated with a specificed width of ${widthArg.get} bits, but at least ${minWidth} bits are required.")
   }
 }