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| author | Andrew Waterman | 2017-02-24 00:33:42 -0800 |
|---|---|---|
| committer | Jack Koenig | 2017-03-08 11:27:04 -0600 |
| commit | 5f846792824cdb467691d929d64de117bb3cffcb (patch) | |
| tree | eb4abdb7c3079ab6188300d081bea17a8e9c83c7 /src/test/scala/chiselTests/Stack.scala | |
| parent | 94c507b1dab33b7b5f4ca864d6b97cbd1682fc7f (diff) | |
Avoid log2Up in tests
Diffstat (limited to 'src/test/scala/chiselTests/Stack.scala')
| -rw-r--r-- | src/test/scala/chiselTests/Stack.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/Stack.scala b/src/test/scala/chiselTests/Stack.scala index 58a05937..df1e68bf 100644 --- a/src/test/scala/chiselTests/Stack.scala +++ b/src/test/scala/chiselTests/Stack.scala @@ -17,7 +17,7 @@ class ChiselStack(val depth: Int) extends Module { }) val stack_mem = Mem(depth, UInt(32.W)) - val sp = Reg(init = 0.U(log2Up(depth+1).W)) + val sp = Reg(init = 0.U(log2Ceil(depth+1).W)) val out = Reg(init = 0.U(32.W)) when (io.en) { |