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| author | Andrew Waterman | 2017-02-24 00:31:36 -0800 |
|---|---|---|
| committer | Jack Koenig | 2017-03-08 11:27:04 -0600 |
| commit | 94c507b1dab33b7b5f4ca864d6b97cbd1682fc7f (patch) | |
| tree | 2ef7e5e65c1ef6a5205849e1883378439d0239bc /src/test/scala/chiselTests/Stack.scala | |
| parent | 4f81b57bce638815de6671c2652095578773e935 (diff) | |
Avoid log2Up in ShiftRegisterTester
This is an odd one. Using log2Ceil directly results in a Verilator
compile error, presumably due to a FIRRTL zero-width wire bug.
Diffstat (limited to 'src/test/scala/chiselTests/Stack.scala')
0 files changed, 0 insertions, 0 deletions