From 5f846792824cdb467691d929d64de117bb3cffcb Mon Sep 17 00:00:00 2001
From: Andrew Waterman
Date: Fri, 24 Feb 2017 00:33:42 -0800
Subject: Avoid log2Up in tests

---
 src/test/scala/chiselTests/Stack.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/test/scala/chiselTests/Stack.scala')

diff --git a/src/test/scala/chiselTests/Stack.scala b/src/test/scala/chiselTests/Stack.scala
index 58a05937..df1e68bf 100644
--- a/src/test/scala/chiselTests/Stack.scala
+++ b/src/test/scala/chiselTests/Stack.scala
@@ -17,7 +17,7 @@ class ChiselStack(val depth: Int) extends Module {
   })
 
   val stack_mem = Mem(depth, UInt(32.W))
-  val sp        = Reg(init = 0.U(log2Up(depth+1).W))
+  val sp        = Reg(init = 0.U(log2Ceil(depth+1).W))
   val out       = Reg(init = 0.U(32.W))
 
   when (io.en) {
-- 
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