Rename packages to lowercase chisel, add compatibility layer

2 files changed, 0 insertions, 106 deletions

diff --git a/src/main/scala/Chisel/testers/BasicTester.scala b/src/main/scala/Chisel/testers/BasicTester.scala
deleted file mode 100644
index b8c1494a..00000000
--- a/src/main/scala/Chisel/testers/BasicTester.scala
+++ /dev/null
@@ -1,38 +0,0 @@
-// See LICENSE for license details.
-
-package Chisel.testers
-import Chisel._
-
-import scala.language.experimental.macros
-
-import internal._
-import internal.Builder.pushCommand
-import internal.firrtl._
-import internal.sourceinfo.SourceInfo
-
-class BasicTester extends Module {
-  // The testbench has no IOs, rather it should communicate using printf, assert, and stop.
-  val io = new Bundle()
-
-  def popCount(n: Long): Int = n.toBinaryString.count(_=='1')
-
-  /** Ends the test reporting success.
-    *
-    * Does not fire when in reset (defined as the encapsulating Module's
-    * reset). If your definition of reset is not the encapsulating Module's
-    * reset, you will need to gate this externally.
-    */
-  def stop()(implicit sourceInfo: SourceInfo) {
-    // TODO: rewrite this using library-style SourceInfo passing.
-    when (!reset) {
-      pushCommand(Stop(sourceInfo, Node(clock), 0))
-    }
-  }
-
-  /** The finish method provides a hook that subclasses of BasicTester can use to
-    * alter a circuit after their constructor has been called.
-    * For example, a specialized tester subclassing BasicTester could override finish in order to
-    * add flow control logic for a decoupled io port of a device under test
-    */
-  def finish(): Unit = {}
-}
diff --git a/src/main/scala/Chisel/testers/TesterDriver.scala b/src/main/scala/Chisel/testers/TesterDriver.scala
deleted file mode 100644
index a56bb8b7..00000000
--- a/src/main/scala/Chisel/testers/TesterDriver.scala
+++ /dev/null
@@ -1,68 +0,0 @@
-// See LICENSE for license details.
-
-package Chisel.testers
-import Chisel._
-import scala.io.Source
-import scala.sys.process._
-import java.io._
-
-object TesterDriver extends BackendCompilationUtilities {
-  /** Copy the contents of a resource to a destination file.
-    */
-  def copyResourceToFile(name: String, file: File) {
-    val in = getClass().getResourceAsStream(name)
-    if (in == null) {
-      throw new FileNotFoundException(s"Resource '$name'")
-    }
-    val out = new FileOutputStream(file)
-    Iterator.continually(in.read).takeWhile(-1 !=).foreach(out.write)
-    out.close()
-  }
-
-  /** For use with modules that should successfully be elaborated by the
-    * frontend, and which can be turned into executables with assertions. */
-  def execute(t: () => BasicTester, additionalVResources: Seq[String] = Seq()): Boolean = {
-    // Invoke the chisel compiler to get the circuit's IR
-    val circuit = Driver.elaborate(finishWrapper(t))
-
-    // Set up a bunch of file handlers based on a random temp filename,
-    // plus the quirks of Verilator's naming conventions
-    val target = circuit.name
-
-    val path = createTempDirectory(target)
-    val fname = new File(path, target)
-
-    // For now, dump the IR out to a file
-    Driver.dumpFirrtl(circuit, Some(new File(fname.toString + ".fir")))
-
-    // Copy CPP harness and other Verilog sources from resources into files
-    val cppHarness =  new File(path, "top.cpp")
-    copyResourceToFile("/top.cpp", cppHarness)
-    val additionalVFiles = additionalVResources.map((name: String) => {
-      val mangledResourceName = name.replace("/", "_")
-      val out = new File(path, mangledResourceName)
-      copyResourceToFile(name, out)
-      out
-    })
-
-    // Use sys.Process to invoke a bunch of backend stuff, then run the resulting exe
-    if ((firrtlToVerilog(target, path) #&&
-        verilogToCpp(target, target, path, additionalVFiles, cppHarness) #&&
-        cppToExe(target, path)).! == 0) {
-      executeExpectingSuccess(target, path)
-    } else {
-      false
-    }
-  }
-  /**
-    * Calls the finish method of an BasicTester or a class that extends it.
-    * The finish method is a hook for code that augments the circuit built in the constructor.
-    */
-  def finishWrapper(test: () => BasicTester): () => BasicTester = {
-    () => {
-      val tester = test()
-      tester.finish()
-      tester
-    }
-  }
-}