diff options
| author | Jim Lawson | 2016-08-17 13:30:05 -0700 |
|---|---|---|
| committer | Jim Lawson | 2016-08-17 13:41:43 -0700 |
| commit | 7922f8d4998dd902ee18a6e85e4a404a1f29eb3f (patch) | |
| tree | acabde9aa9c81dc3620dc501f89bcb674bdfe19b /chiselFrontend/src/main/scala/chisel3/core/Binding.scala | |
| parent | f41f2533c55e506f7d5bf2ee0198de4d9a3dbea3 (diff) | |
Rocket-chip updates.
Assume LHSItOutput if neither side is driving.
Restore Wire()'s removal of direction in binding.
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core/Binding.scala')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/Binding.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Binding.scala b/chiselFrontend/src/main/scala/chisel3/core/Binding.scala index 555ba4d5..da678fed 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Binding.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Binding.scala @@ -207,5 +207,5 @@ case class PortBinding(enclosure: Module, direction: Option[Direction]) case class RegBinding(enclosure: Module) extends SynthesizableBinding with ConstrainedBinding with UndirectionedBinding -case class WireBinding(enclosure: Module, direction: Option[Direction]) - extends SynthesizableBinding with ConstrainedBinding +case class WireBinding(enclosure: Module) + extends SynthesizableBinding with ConstrainedBinding with UndirectionedBinding |