diff options
| author | Jim Lawson | 2016-08-17 13:30:05 -0700 |
|---|---|---|
| committer | Jim Lawson | 2016-08-17 13:41:43 -0700 |
| commit | 7922f8d4998dd902ee18a6e85e4a404a1f29eb3f (patch) | |
| tree | acabde9aa9c81dc3620dc501f89bcb674bdfe19b /chiselFrontend/src/main/scala/chisel3/core | |
| parent | f41f2533c55e506f7d5bf2ee0198de4d9a3dbea3 (diff) | |
Rocket-chip updates.
Assume LHSItOutput if neither side is driving.
Restore Wire()'s removal of direction in binding.
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core')
3 files changed, 10 insertions, 5 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala b/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala index b7fd65a5..c40b85ad 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala @@ -188,7 +188,13 @@ object BiConnect { throw BothDriversException } } - case (None, None) => throw UnknownDriverException + case (None, None) => { + if (compileOptions.assumeLHSIsOutput) { + issueConnectR2L(left, right) + } else { + throw UnknownDriverException + } + } } } diff --git a/chiselFrontend/src/main/scala/chisel3/core/Binder.scala b/chiselFrontend/src/main/scala/chisel3/core/Binder.scala index 08c0519e..c7346dce 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Binder.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Binder.scala @@ -58,8 +58,7 @@ case class RegBinder(enclosure: Module) extends Binder[RegBinding] { def apply(in: UnboundBinding) = RegBinding(enclosure) } -// Notice how WireBinder uses the direction of the UnboundNode case class WireBinder(enclosure: Module) extends Binder[WireBinding] { - def apply(in: UnboundBinding) = WireBinding(enclosure, in.direction) + def apply(in: UnboundBinding) = WireBinding(enclosure) } diff --git a/chiselFrontend/src/main/scala/chisel3/core/Binding.scala b/chiselFrontend/src/main/scala/chisel3/core/Binding.scala index 555ba4d5..da678fed 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Binding.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Binding.scala @@ -207,5 +207,5 @@ case class PortBinding(enclosure: Module, direction: Option[Direction]) case class RegBinding(enclosure: Module) extends SynthesizableBinding with ConstrainedBinding with UndirectionedBinding -case class WireBinding(enclosure: Module, direction: Option[Direction]) - extends SynthesizableBinding with ConstrainedBinding +case class WireBinding(enclosure: Module) + extends SynthesizableBinding with ConstrainedBinding with UndirectionedBinding |