diff options
| author | Jim Lawson | 2016-08-17 13:30:05 -0700 |
|---|---|---|
| committer | Jim Lawson | 2016-08-17 13:41:43 -0700 |
| commit | 7922f8d4998dd902ee18a6e85e4a404a1f29eb3f (patch) | |
| tree | acabde9aa9c81dc3620dc501f89bcb674bdfe19b /chiselFrontend/src/main/scala/chisel3/core/Binder.scala | |
| parent | f41f2533c55e506f7d5bf2ee0198de4d9a3dbea3 (diff) | |
Rocket-chip updates.
Assume LHSItOutput if neither side is driving.
Restore Wire()'s removal of direction in binding.
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core/Binder.scala')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/Binder.scala | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Binder.scala b/chiselFrontend/src/main/scala/chisel3/core/Binder.scala index 08c0519e..c7346dce 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Binder.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Binder.scala @@ -58,8 +58,7 @@ case class RegBinder(enclosure: Module) extends Binder[RegBinding] { def apply(in: UnboundBinding) = RegBinding(enclosure) } -// Notice how WireBinder uses the direction of the UnboundNode case class WireBinder(enclosure: Module) extends Binder[WireBinding] { - def apply(in: UnboundBinding) = WireBinding(enclosure, in.direction) + def apply(in: UnboundBinding) = WireBinding(enclosure) } |