diff options
| author | Jim Lawson | 2016-08-16 11:59:20 -0700 |
|---|---|---|
| committer | Jim Lawson | 2016-08-17 13:41:43 -0700 |
| commit | f41f2533c55e506f7d5bf2ee0198de4d9a3dbea3 (patch) | |
| tree | 4a9786dd4e468d9517517603b06b123e1e35b44f /chiselFrontend/src/main/scala/chisel3/core/Binder.scala | |
| parent | a264157a47f56216cebf2d98c1c8118c344dad5f (diff) | |
Reduce rocket-chip elaboration errors.
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core/Binder.scala')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/Binder.scala | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Binder.scala b/chiselFrontend/src/main/scala/chisel3/core/Binder.scala index c7346dce..08c0519e 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Binder.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Binder.scala @@ -58,7 +58,8 @@ case class RegBinder(enclosure: Module) extends Binder[RegBinding] { def apply(in: UnboundBinding) = RegBinding(enclosure) } +// Notice how WireBinder uses the direction of the UnboundNode case class WireBinder(enclosure: Module) extends Binder[WireBinding] { - def apply(in: UnboundBinding) = WireBinding(enclosure) + def apply(in: UnboundBinding) = WireBinding(enclosure, in.direction) } |