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2015-08-17Fixed bug where equality between expressions was incorrect, leading toazidar
an optimization that eliminated some when statements. Added test case.
2015-08-17Added tests for shl and mem. Fixed bug in verilog output of mem size.azidar
2015-08-04Added check for reading from outputs with flipsazidar
2015-08-03Changed name mangling to use _ as a delin. Fixed bug in checking forazidar
invalid <> assignments.
2015-08-03Fixed performance bug in Split Expressions. Changed delin for connect ↵azidar
indexed. Fixed various broken tests.
2015-07-31Updated tests to pipe from stderr to stdoutazidar
2015-07-30Updated error and feature tests. Fixed bug in detecting incorrect gendersazidar
2015-07-30Added eqv for bitwise equality, and change eq to be arithmetic equalityazidar
2015-07-30Updated lots of tests so they pass. Found one bug in expand whensazidar
2015-07-14Added tests for clocks. Added remove scope and special chars passes. Added ↵azidar
tests. Made more tests pass
2015-07-14Added clock supportazidar
2015-07-14Pass most tests. The ones that do not pass are not expected to, yetazidar
2015-07-14Still partial commit, many tests pass. Many tests fail.azidar
2015-07-14In progress commitazidar
2015-06-12Major revisions to spec. Bumped to v0.1.2azidar
2015-05-27Added sequential memories. mem no longer exists, must declare either cmem or ↵azidar
smem. Added firrtl-gensym utility to generate a hashmap of names
2015-05-27Added external modules. Switched lower firrtl back to wire r; r := Register, ↵azidar
instead of using nodes. Added a renaming pass for different backends. This will likely get deprecated, as a more robust name mangling scheme could be needed
2015-05-26Added <>. Added additional checks for primops. Added new chisel3 files.azidar
2015-05-20Added Pad pass to flo.stanza, which pads widths to make := and primops ↵azidar
strict. Have not tested this
2015-05-19Updated testsazidar
2015-05-18First pass at a Verilog Backend. Not tested, but compiles and generates ↵azidar
reasonable verilog. Requires inlining, future versions will instantiate modules
2015-05-18Big API Change. Pad is no longer supported. Widths of primops can be ↵azidar
flexible, and the output is usually the max of the inputs. Removed all u/s variants, which need to be dealt with in backends where it matters
2015-05-15Updated firrtl for its passes to be a bit more modular, and to enable ↵azidar
plugging in other backends. Also updated a lot of tests, but not all of them because its annoying.
2015-05-13Added source indicators from FIRRTL files. Pass in -p i to get them printed. ↵azidar
Should show up with check passes
2015-05-13Updated Spec. Added scoped-reg which exposes on-reset bug. Fixed lowering bugazidar
2015-05-02Now when expanding ConnectFrom/ToIndex, create a node for the index so it ↵azidar
isn't duplicated for all the whens
2015-05-01Bug fix. ExpWidth was improperly evaluated during simplify (not subtracting one)azidar
2015-04-30Fixed assignment to outputs not getting emitted from Expand When passazidar
2015-04-29Fixed bug where a node's width was not equal to its value'sazidar
2015-04-29Added dshl and dshrazidar
2015-04-28Instances are now male. Reworked lowering pass to be sane. ↵azidar
chisel3/ModuleVec.fir doesn't work because incorrecly generated?
2015-04-27Added on-resetazidar
2015-04-24Merge branch 'master' of github.com:ucb-bar/firrtl into parserazidar
Conflicts: TODO src/main/stanza/passes.stanza
2015-04-24Fixed width inference bug where later constraints on the output width were ↵azidar
not propogating to the input widths, for primops
2015-04-24Fixed performance bug in expand-when where equality between the consequence ↵azidar
and alternate were always assumed different, causing a huge blow-up in logic
2015-04-23Fixed bug in lowering where the arguments to DoPrim and Pad weren't loweredazidar
2015-04-23Not finished commmitazidar
2015-04-23Added new parser. Fixed all Tests. Added on-reset to parser, but don't ↵azidar
correctly handle it in compiler.
2015-04-23Fixed Pad inference bugazidar
2015-04-22Switched to stricter primop width constraints. Implemented Pad. Added some ↵azidar
missing primops
2015-04-21Reordered resolve-kinds and make-explicit-reset to fix bug where reset, if ↵azidar
referenced, has an inferred kind
2015-04-20Fixed tests to use new execution arguments. Added and fixed chisel3 bugsazidar
2015-04-17Removed excessive debug print statements, added default call to firrtl to ↵azidar
generate flo
2015-04-17Added temp elimination passazidar
2015-04-17Fixed bug in primop lowering during type inference. Added reduce ↵azidar
instructions and renamed concat -> cat, equal -> eq, and added neq and neg
2015-04-16Merged with new stanzaazidar
2015-04-15Finished flo backend. Restructured todo listazidar
2015-04-14Finished Split Expressionsazidar
2015-04-14Finished inlining passazidar
2015-04-13Stanza bugazidar