sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Collapse)	Author
2016-01-25	Changed tests to pass with change to postfix of generated name	azidar

2016-01-16	Fixed all tests so they either pass are marked as expected failures	azidar

2016-01-16	Fixed a bunch of tests, and minor bugs	azidar

2016-01-16	WIP. Fixed a bunch of tests. Starting on implementing chirrtl, but hit ↵	azidar
	roadblock in assigning clocked ports
2016-01-16	New memory works with verilog. Slowly changing tests and fixing bugs.	azidar
	Decided to not have Conditionally in low firrtl - instead, Print and Stop have enables
2015-09-30	Fixed naming bug where __1 was matching. Caused lots o issues.	azidar

2015-08-25	Fixed bug in split expression that leaked connect statements out of a ↵	azidar
	conditional assignment
2015-08-24	Changed all tests to use verilog backend.	azidar

2015-08-03	Changed name mangling to use _ as a delin. Fixed bug in checking for	azidar
	invalid <> assignments.
2015-07-31	Updated tests to pipe from stderr to stdout	azidar

2015-07-14	Added tests for clocks. Added remove scope and special chars passes. Added ↵	azidar
	tests. Made more tests pass
2015-05-18	Big API Change. Pad is no longer supported. Widths of primops can be ↵	azidar
	flexible, and the output is usually the max of the inputs. Removed all u/s variants, which need to be dealt with in backends where it matters
2015-04-23	Added new parser. Fixed all Tests. Added on-reset to parser, but don't ↵	azidar
	correctly handle it in compiler.
2015-04-20	Fixed tests to use new execution arguments. Added and fixed chisel3 bugs	azidar

2015-04-17	Fixed bug in primop lowering during type inference. Added reduce ↵	azidar
	instructions and renamed concat -> cat, equal -> eq, and added neq and neg
2015-04-14	Finished Split Expressions	azidar