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authorazidar2015-08-03 18:39:55 -0700
committerazidar2015-08-03 18:39:55 -0700
commitff6dfecf42560ed2e2eb678adc9ca8d868a472bd (patch)
tree1483818b3efa226bce74cca560f1aa38102ebcfa /test/passes/split-exp
parentec3bf6a6a74061721024dece229f7a6062f5c7fc (diff)
Changed name mangling to use _ as a delin. Fixed bug in checking for
invalid <> assignments.
Diffstat (limited to 'test/passes/split-exp')
-rw-r--r--test/passes/split-exp/primop.fir21
1 files changed, 21 insertions, 0 deletions
diff --git a/test/passes/split-exp/primop.fir b/test/passes/split-exp/primop.fir
new file mode 100644
index 00000000..3b120217
--- /dev/null
+++ b/test/passes/split-exp/primop.fir
@@ -0,0 +1,21 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+
+;CHECK: Split Expressions
+circuit Top :
+ module Top :
+ output out : UInt<1>
+ output out2 : UInt<1>
+
+ wire m : UInt<1>[3]
+ m[0] := UInt(0)
+ m[1] := UInt(0)
+ m[2] := UInt(0)
+
+ wire x : UInt<1>
+ x := not(UInt(1))
+ infer accessor a = m[x]
+
+ out := a
+
+
+