| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2016-01-16 | Fixed all tests so they either pass are marked as expected failures | azidar | |
| 2016-01-16 | New memory works with verilog. Slowly changing tests and fixing bugs. | azidar | |
| Decided to not have Conditionally in low firrtl - instead, Print and Stop have enables | |||
| 2016-01-16 | WIP need to correctly output readwrite ports | azidar | |
| 2015-09-29 | Fixed final bug. All tests pass. Accessors are a go. | azidar | |
| 2015-09-29 | Added DecToIndexer/DecFromIndexer. Fixed most use cases of incorrect ↵ | azidar | |
| catching of initialization of accessors. Missing use case of accessing an accessor. Still need to update tests to pass | |||
