| Age | Commit message (Expand) | Author |
|---|---|---|
| 2016-08-15 | Remove stanza (#231) | Adam Izraelevitz |
| 2016-01-16 | New memory works with verilog. Slowly changing tests and fixing bugs. | azidar |
| 2015-08-24 | Changed all tests to use verilog backend. | azidar |
| 2015-07-31 | Updated tests to pipe from stderr to stdout | azidar |
| 2015-07-14 | Pass most tests. The ones that do not pass are not expected to, yet | azidar |
| 2015-05-18 | Big API Change. Pad is no longer supported. Widths of primops can be flexible... | azidar |
| 2015-05-15 | Updated firrtl for its passes to be a bit more modular, and to enable pluggin... | azidar |
| 2015-05-01 | Bug fix. ExpWidth was improperly evaluated during simplify (not subtracting one) | azidar |
| 2015-04-29 | Added dshl and dshr | azidar |
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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