sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Expand)	Author
2016-01-17	BIT-AND, BIT-OR, and BIT-XOR now can accept SInts. Fixed tests	azidar
2016-01-16	WIP. Fixed a bunch of tests. Starting on implementing chirrtl, but hit roadbl...	azidar
2016-01-16	New memory works with verilog. Slowly changing tests and fixing bugs.	azidar
2015-08-24	Changed all tests to use verilog backend.	azidar
2015-07-31	Updated tests to pipe from stderr to stdout	azidar
2015-07-14	Added tests for clocks. Added remove scope and special chars passes. Added te...	azidar
2015-07-14	Still partial commit, many tests pass. Many tests fail.	azidar
2015-05-27	Added sequential memories. mem no longer exists, must declare either cmem or ...	azidar
2015-05-15	Updated firrtl for its passes to be a bit more modular, and to enable pluggin...	azidar
2015-04-23	Added new parser. Fixed all Tests. Added on-reset to parser, but don't correc...	azidar
2015-04-20	Fixed tests to use new execution arguments. Added and fixed chisel3 bugs	azidar
2015-03-27	Corrected register init by adding initialization of registers pass after lowe...	azidar
2015-03-23	Finished first two parts of expand-whens pass. Fixed inits by adding WRegInit...	azidar
2015-03-18	Finished expand accessors and lower to ground	azidar