| Age | Commit message (Expand) | Author |
|---|---|---|
| 2016-08-15 | Remove stanza (#231) | Adam Izraelevitz |
| 2016-02-09 | Changed stanza output of UInt/SInt to include widths. Made tests match accord... | azidar |
| 2016-01-28 | Updated all tests to pass | azidar |
| 2016-01-16 | WIP. Fixed a bunch of tests. Starting on implementing chirrtl, but hit roadbl... | azidar |
| 2016-01-16 | New memory works with verilog. Slowly changing tests and fixing bugs. | azidar |
| 2015-08-24 | Changed all tests to use verilog backend. | azidar |
| 2015-08-18 | Fixed so its length is greater than what it connects to. Changed shr to be e... | azidar |
| 2015-07-31 | Updated tests to pipe from stderr to stdout | azidar |
| 2015-07-30 | Updated lots of tests so they pass. Found one bug in expand whens | azidar |
| 2015-07-14 | Added tests for clocks. Added remove scope and special chars passes. Added te... | azidar |
| 2015-07-14 | In progress commit | azidar |
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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