sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Expand)	Author
2016-08-15	Remove stanza (#231)	Adam Izraelevitz
2016-02-09	Changed stanza output of UInt/SInt to include widths. Made tests match accord...	azidar
2016-01-28	Updated all tests to pass	azidar
2016-01-16	WIP. Fixed a bunch of tests. Starting on implementing chirrtl, but hit roadbl...	azidar
2016-01-16	New memory works with verilog. Slowly changing tests and fixing bugs.	azidar
2015-08-24	Changed all tests to use verilog backend.	azidar
2015-08-18	Fixed so its length is greater than what it connects to. Changed shr to be e...	azidar
2015-07-31	Updated tests to pipe from stderr to stdout	azidar
2015-07-30	Updated lots of tests so they pass. Found one bug in expand whens	azidar
2015-07-14	Added tests for clocks. Added remove scope and special chars passes. Added te...	azidar
2015-07-14	Still partial commit, many tests pass. Many tests fail.	azidar
2015-05-27	Added external modules. Switched lower firrtl back to wire r; r := Register, ...	azidar
2015-05-20	Added Pad pass to flo.stanza, which pads widths to make := and primops strict...	azidar
2015-05-18	Big API Change. Pad is no longer supported. Widths of primops can be flexible...	azidar
2015-05-15	Updated firrtl for its passes to be a bit more modular, and to enable pluggin...	azidar
2015-04-27	Added on-reset	azidar