| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2020-09-16 | Change to Apache 2.0 License (#1901) | Chick Markley | |
| 2020-07-27 | Update RightShiftTests.fir to avoid buggy Counter pattern | Albert Magyar | |
| * See freechipsproject/chisel3#1408 | |||
| 2016-12-08 | Clk2clock - rename the implicit "clk" module input "clock" (#387) | Jim Lawson | |
| * Rename implict module "clk" input to "clock". This doesn't rename all the "self-contained" test instances. nor the memory "clk" enables, nor the implict module "clk"s in the regress .fir files. * Consistency: rename implict module "clk" input to "clock" in "self-contained" test instances. This doesn't rename the memory "clk" enables, nor the implict module "clk"s in the regress .fir files. | |||
| 2016-03-10 | Add support for right shift by amount larger than argument width | jackkoenig | |
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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