| Age | Commit message (Expand) | Author |
|---|---|---|
| 2016-01-24 | Added muxing on passive aggregate types | azidar |
| 2016-01-16 | Fixed a bunch of tests, and minor bugs | azidar |
| 2016-01-16 | WIP. Fixed a bunch of tests. Starting on implementing chirrtl, but hit roadbl... | azidar |
| 2016-01-16 | Finished supporting nested accesses. Required some nuianced thinking. Pass al... | azidar |
| 2016-01-16 | New memory works with verilog. Slowly changing tests and fixing bugs. | azidar |
| 2015-08-24 | Changed all tests to use verilog backend. | azidar |
| 2015-08-20 | Added tests, cleaned up repo | azidar |
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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