diff options
| author | azidar | 2015-08-24 11:45:37 -0700 |
|---|---|---|
| committer | azidar | 2015-08-24 11:45:37 -0700 |
| commit | 5d3061bfed8445370e6fa97ec9238ba49e8fafbc (patch) | |
| tree | ba0373c05118215fa332c9e7cd10233a69800f53 /test/features/InitAccessor.fir | |
| parent | 50cf7a4823d69967dcb2b10cdef892b0ab5f2184 (diff) | |
Changed all tests to use verilog backend.
Diffstat (limited to 'test/features/InitAccessor.fir')
| -rw-r--r-- | test/features/InitAccessor.fir | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/test/features/InitAccessor.fir b/test/features/InitAccessor.fir index 983cbd94..0bf861f2 100644 --- a/test/features/InitAccessor.fir +++ b/test/features/InitAccessor.fir @@ -1,9 +1,13 @@ -; RUN: firrtl -i %s -o %s.flo -X flo -p c 2>&1 | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s +; XFAIL: * ;CHECK: Done! circuit Top : module Top : input in : UInt<1> wire b : UInt<1>[3] + b.0 := UInt(1) + b.1 := UInt(1) + b.2 := UInt(1) node c = UInt(1) infer accessor a = b[c] when in : |