| Age | Commit message (Expand) | Author |
|---|---|---|
| 2016-01-16 | New memory works with verilog. Slowly changing tests and fixing bugs. | azidar |
| 2015-07-31 | Updated tests to pipe from stderr to stdout | azidar |
| 2015-07-30 | Updated lots of tests so they pass. Found one bug in expand whens | azidar |
| 2015-05-27 | Added external modules. Switched lower firrtl back to wire r; r := Register, ... | azidar |
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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