Added external modules. Switched lower firrtl back to wire r; r := Register, instead of using nodes. Added a renaming pass for different backends. This will likely get deprecated, as a more robust name mangling scheme could be needed

1 files changed, 14 insertions, 0 deletions

diff --git a/test/features/ExModule.fir b/test/features/ExModule.fir
new file mode 100644
index 00000000..b47b14ab
--- /dev/null
+++ b/test/features/ExModule.fir
@@ -0,0 +1,14 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
+circuit Top : 
+  module Top : 
+    output z : UInt<4>
+    inst i of BlackBox
+    i.x := UInt(1)
+    i.y := UInt(2)
+    z := i.z
+  exmodule BlackBox :
+    input x : UInt<4>
+    input y : UInt<4>
+    output z : UInt<4>
+
+;CHECK: Done!