sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Expand)	Author
2016-01-16	WIP. Fixed a bunch of tests. Starting on implementing chirrtl, but hit roadbl...	azidar
2016-01-16	New memory works with verilog. Slowly changing tests and fixing bugs.	azidar
2015-08-24	Changed all tests to use verilog backend.	azidar
2015-07-31	Added errors for bulk connects where field names match but types/flips don't	azidar
2015-07-31	Updated tests to pipe from stderr to stdout	azidar
2015-07-14	Pass most tests. The ones that do not pass are not expected to, yet	azidar
2015-05-27	Added sequential memories. mem no longer exists, must declare either cmem or ...	azidar
2015-05-26	Added <>. Added additional checks for primops. Added new chisel3 files.	azidar