sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Expand)	Author
2015-08-03	Changed name mangling to use _ as a delin. Fixed bug in checking for	azidar
2015-08-03	Fixed performance bug in Split Expressions. Changed delin for connect indexed...	azidar
2015-07-31	Reading from output ports no longer causes errors	azidar
2015-07-31	Added errors for bulk connects where field names match but types/flips don't	azidar
2015-07-31	Updated tests to pipe from stderr to stdout	azidar
2015-07-30	Added module name to error messages.	azidar
2015-07-30	Updated error and feature tests. Fixed bug in detecting incorrect genders	azidar
2015-07-14	Added tests for clocks. Added remove scope and special chars passes. Added te...	azidar
2015-07-14	Pass most tests. The ones that do not pass are not expected to, yet	azidar
2015-06-02	Added sequential/combinational memories. Started debugging verilog backend. A...	azidar
2015-05-27	Added sequential memories. mem no longer exists, must declare either cmem or ...	azidar
2015-05-26	Added <>. Added additional checks for primops. Added new chisel3 files.	azidar
2015-05-20	Added Pad pass to flo.stanza, which pads widths to make := and primops strict...	azidar
2015-05-05	Added a bunch of tests. In the middle of implementing check kinds and check t...	azidar
2015-05-02	Added a infrastructure for check passes, and wrote a few	azidar