| Age | Commit message (Expand) | Author |
|---|---|---|
| 2016-01-28 | Updated all tests to pass | azidar |
| 2016-01-16 | Fixed a bunch of tests, and minor bugs | azidar |
| 2016-01-16 | New memory works with verilog. Slowly changing tests and fixing bugs. | azidar |
| 2015-08-20 | Added tests, cleaned up repo | azidar |
| 2015-08-04 | Added verilog keywords to uniquify them | azidar |
| 2015-08-04 | Fixed reading from instance's input ports. Fixed unique naming bug. | azidar |
| 2015-08-03 | Changed name mangling to use _ as a delin. Fixed bug in checking for | azidar |
| 2015-08-03 | Fixed performance bug in Split Expressions. Changed delin for connect indexed... | azidar |
| 2015-07-31 | Reading from output ports no longer causes errors | azidar |
| 2015-07-31 | Updated tests to pipe from stderr to stdout | azidar |
| 2015-07-30 | Updated error and feature tests. Fixed bug in detecting incorrect genders | azidar |
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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