sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Expand)	Author
2015-05-26	Added <>. Added additional checks for primops. Added new chisel3 files.	azidar
2015-05-21	Added pad pass, used for flo backend	azidar
2015-05-13	Added source indicators from FIRRTL files. Pass in -p i to get them printed. ...	azidar
2015-05-13	Updated Spec. Added scoped-reg which exposes on-reset bug. Fixed lowering bug	azidar
2015-05-04	Added new Control.fir with reduced padding	azidar
2015-05-04	Fixed bug where instance types were not lowered	azidar
2015-05-04	Updated stuff	azidar
2015-05-04	Fixed change where type of mux-ss was incorrect	azidar
2015-05-02	Added a infrastructure for check passes, and wrote a few	azidar
2015-05-02	Now when expanding ConnectFrom/ToIndex, create a node for the index so it isn...	azidar
2015-05-01	Fixed performance bug where PlusWidth, MinusWidth, and ExpWidth could be simp...	azidar
2015-05-01	Fixed bug where the enable was looked at for lowering MUX.	azidar
2015-04-29	Fixed bug in lowering of subfields. Fixed ModuleVec.fir to be correct	azidar
2015-04-28	Instances are now male. Reworked lowering pass to be sane. chisel3/ModuleVec....	azidar
2015-04-22	Added new test that breaks current parser. updated todo	azidar
2015-04-21	Added new test	azidar
2015-04-20	Fixed tests to use new execution arguments. Added and fixed chisel3 bugs	azidar
2015-04-16	Updated parser to correctly read empty statements	azidar
2015-04-13	new chisel3 tests	jackbackrack