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but not Emitter. (#717)
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* Changed primops to not accept mixed-type args
* Changed return type of sub of two uints to uint
* Added negative tests
* Removed rocket.fir. Manually changed RocketCore to not mix mul arg types. Added integration tests
* Clarified test description and remove println
* Fixed use of throwInternalError
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* Catch exceptions and convert to internal error.
We need to update the displayed message to incorporate a line number and text to be used for the issue.
* Cleanup exception handling/throwing.
Re-throw expected (or uncorrectable exceptions).
Provide Utils.getThrowable() to get the first (eldest) or last throwable in the chain.
Update tests to conform to FreeSpec protocol.
* Minor cleanup
Admit we've updated some deprecated ScalaTest methods.
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Fixes #700
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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A circuit with a single module would fail to properly compute BV RMQs due
to a divide by zero bug.
This changes the computation of the number of blocks an Euler Tour is
broken up into to be, at minimum, one.
This also changes one of the test cases ("wire with source and sink in the
same module") to exercise this.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Two instances of the same module could collide in counting the number of
instances of each Module. This could lead to constants being propagated
on inputs when it is incorrect to do so.
Fixes #734
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Massive refactoring to WiringTransform with the use of a new EulerTour
class to speed things up via fast least common ancestor (LCA) queries.
Changes include (but are not limited to):
* Use lowest common ancestor when wiring
* Add EulerTour class with naive and Berkman-Vishkin RMQ
* Adds LCA method for Instance Graph
* Enables "Two Sources" using "Top" wiring test as this is now valid
* Remove TopAnnotation from WiringTransform
* Represent WiringTransform sink as `Seq[Named]`
* Remove WiringUtils.countInstances, fix imports
* Support sources under sinks in WiringTransform
* Enable internal module wiring
* Support Wiring of Aggregates
h/t @edcote
fixes #728
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Reviewed-by: Jack Koenig<jack.koenig3@gmail.com>
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Fix FirrtlExecutionOptions backward incompatible change (#704).
New options should be added to the end of the list to reduce backward compatibility problems.
Update comment to mention backwards compatibility issue.
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Change loadAnnotations to return annotations instead of mutating firrtlOptions
Deprecate implicit annotation file (top.anno) and annotation file override
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The logic around this option was unintuitive and led to silently dropped
annotations.
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[skip formal checks]
Generate nicer name for remove accesses
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Fixes #527
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This resulted in parent modules sometimes being constant proppagated
before a child module. If the child module has a constant driving one of
its outputs, the parent module would thus not see the constant. This
resulted in strange unstable constant propagation behavior where
sometimes constant outputs would not propagate.
Also add test illustrating why this occurs with uses of InstanceGraph
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Fixes #708
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This transform replaces all wires with nodes in a legal, flow-forward
order
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Move pad to object ConstantPropagation so other transforms can use it
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* add graph node classes
* add graph representation usage pass
* remove pass using graph nodes so that firrtl can compile
* move google graph ir nodes to altIR package
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Defined as the range from ' ' to '~' [0x20, 0x7e]
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This prevents collisions for one prefix (including temp) from
incrementing the suffix for other prefixes. Makes names more stable.
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Refactor StringLit to use String instead of Array[Byte]
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When calling verilator in a subdirectory like ./test_run_dir/...
verilator will read the verilog file from the current working directory
if there is a file there with the right name. This fix specifies
the specific path of the verilog file intended.
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not exit when --help is included in program flags
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Adds programArgs to commonOptions
programArgs is all arguments on command line with out leading -/+
or are not bound to a flag.
Create simple test
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* Make pathsInDAG walk all possible paths
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
* Use linearization order when finding all paths in DAG
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