diff options
| author | Jack Koenig | 2018-01-30 12:53:56 -0800 |
|---|---|---|
| committer | Jack Koenig | 2018-01-30 12:53:56 -0800 |
| commit | c9d3e257bff74235a75ff5530051e419b9ce8005 (patch) | |
| tree | 70de3e10760efef858ca78a4e181e28d30984abe /src | |
| parent | 8bdc969f95571fa22b39612d3e3acc69268cf2f0 (diff) | |
Make Constant Propagation respect dontTouch on registers
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/firrtl/transforms/ConstantPropagation.scala | 2 | ||||
| -rw-r--r-- | src/test/scala/firrtlTests/ConstantPropagationTests.scala | 15 |
2 files changed, 16 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/transforms/ConstantPropagation.scala b/src/main/scala/firrtl/transforms/ConstantPropagation.scala index b767ef65..d08a7e6b 100644 --- a/src/main/scala/firrtl/transforms/ConstantPropagation.scala +++ b/src/main/scala/firrtl/transforms/ConstantPropagation.scala @@ -367,7 +367,7 @@ class ConstantPropagation extends Transform { // Const prop registers that are fed only a constant or a mux between and constant and the // register itself // This requires that reset has been made explicit - case Connect(_, lref @ WRef(lname, ltpe, RegKind, _), expr) => expr match { + case Connect(_, lref @ WRef(lname, ltpe, RegKind, _), expr) if !dontTouches.contains(lname) => expr match { case lit: Literal => nodeMap(lname) = constPropExpression(pad(lit, ltpe)) case Mux(_, tval: WRef, fval: Literal, _) if weq(lref, tval) => diff --git a/src/test/scala/firrtlTests/ConstantPropagationTests.scala b/src/test/scala/firrtlTests/ConstantPropagationTests.scala index 2aad4f21..e143f853 100644 --- a/src/test/scala/firrtlTests/ConstantPropagationTests.scala +++ b/src/test/scala/firrtlTests/ConstantPropagationTests.scala @@ -712,6 +712,21 @@ class ConstantPropagationIntegrationSpec extends LowTransformSpec { execute(input, check, Seq(dontTouch("Top.z"))) } + "ConstProp" should "NOT optimize across dontTouch on registers" in { + val input = + """circuit Top : + | module Top : + | input clk : Clock + | input reset : UInt<1> + | output y : UInt<1> + | reg z : UInt<1>, clk + | y <= z + | z <= mux(reset, UInt<1>("h0"), z)""".stripMargin + val check = input + execute(input, check, Seq(dontTouch("Top.z"))) + } + + it should "NOT optimize across dontTouch on wires" in { val input = """circuit Top : |
