diff options
| author | Jack Koenig | 2017-06-15 10:33:39 -0700 |
|---|---|---|
| committer | Adam Izraelevitz | 2017-12-29 11:41:07 -0800 |
| commit | ea6237c3bf02bb9f0f89f573831f09898bef14b0 (patch) | |
| tree | 5e8724c2a6fce74f04ab70e0f3f45194443ae417 /src | |
| parent | a976ba219f02cea49cdaf9446a691a3731dfa31b (diff) | |
Add logger printing for declarations removed by DCE
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/firrtl/transforms/DeadCodeElimination.scala | 37 |
1 files changed, 34 insertions, 3 deletions
diff --git a/src/main/scala/firrtl/transforms/DeadCodeElimination.scala b/src/main/scala/firrtl/transforms/DeadCodeElimination.scala index 578de264..22e7da6e 100644 --- a/src/main/scala/firrtl/transforms/DeadCodeElimination.scala +++ b/src/main/scala/firrtl/transforms/DeadCodeElimination.scala @@ -180,6 +180,24 @@ class DeadCodeElimination extends Transform { moduleMap: collection.Map[String, DefModule], renames: RenameMap) (mod: DefModule): Option[DefModule] = { + // For log-level debug + def deleteMsg(decl: IsDeclaration): String = { + val tpe = decl match { + case _: DefNode => "node" + case _: DefRegister => "reg" + case _: DefWire => "wire" + case _: Port => "port" + case _: DefMemory => "mem" + case (_: DefInstance | _: WDefInstance) => "inst" + case _: Module => "module" + case _: ExtModule => "extmodule" + } + val ref = decl match { + case (_: Module | _: ExtModule) => mod.name + case _ => s"${mod.name}.${decl.name}" + } + s"[DCE] $tpe $ref" + } def getDeps(expr: Expression): Seq[LogicNode] = getDepsImpl(mod.name, instMap)(expr) var emptyBody = true @@ -191,12 +209,14 @@ class DeadCodeElimination extends Transform { moduleMap.get(inst.module) match { case Some(instMod) => inst.copy(tpe = Utils.module_type(instMod)) case None => + logger.debug(deleteMsg(inst)) renames.delete(inst.name) EmptyStmt } case decl: IsDeclaration => val node = LogicNode(mod.name, decl.name) if (deadNodes.contains(node)) { + logger.debug(deleteMsg(decl)) renames.delete(decl.name) EmptyStmt } @@ -221,14 +241,25 @@ class DeadCodeElimination extends Transform { } val (deadPorts, portsx) = mod.ports.partition(p => deadNodes.contains(LogicNode(mod.name, p.name))) - deadPorts.foreach(p => renames.delete(p.name)) + deadPorts.foreach { p => + logger.debug(deleteMsg(p)) + renames.delete(p.name) + } mod match { case Module(info, name, _, body) => val bodyx = onStmt(body) - if (emptyBody && portsx.isEmpty) None else Some(Module(info, name, portsx, bodyx)) + if (emptyBody && portsx.isEmpty) { + logger.debug(deleteMsg(mod)) + None + } else { + Some(Module(info, name, portsx, bodyx)) + } case ext: ExtModule => - if (portsx.isEmpty) None + if (portsx.isEmpty) { + logger.debug(deleteMsg(mod)) + None + } else { if (ext.ports != portsx) throwInternalError // Sanity check Some(ext.copy(ports = portsx)) |
