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AgeCommit message (Expand)Author
2018-05-30Makes ExpandWhens preserve connect Infoschick
2018-05-29Fix pad (#817)Jack Koenig
2018-05-23Add Circuit as option to FirrtlOptions (#814)Jack Koenig
2018-05-21Fix more problems with zero width things. (#779)grebe
2018-05-15Don't use bash to determine command availability - fixes #807 (#808)Jim Lawson
2018-05-15Replace truncating add and sub with addw/subw (#800)Jack Koenig
2018-05-11TopWiring Transform (#798)alonamid
2018-05-09Bugfix: ports of a temporary name would break const-prop (#806)Adam Izraelevitz
2018-05-02Deprecate old WiringUtils methods/classes (#801)Schuyler Eldridge
2018-04-29Fix pathological behavior of Namespace for name collisions (#788)Jack Koenig
2018-04-26Fix bug in VerilogMemDelays (#795)Jack Koenig
2018-04-16Cleaning up BlackBoxSourceHelper - use absolute file paths. (#789)Jim Lawson
2018-04-13Remove infinitely recursive function (#790)Jack Koenig
2018-04-11Cleaning up BlackBoxSourceHelper (#786)Henry Cook
2018-04-11Make DiGraph.linearize be iterative instead of recursive (#785)Jack Koenig
2018-04-10Fix bug in Constant Propagation for registers propped to zero (#787)Jack Koenig
2018-04-03Make Dedup properly dedup ExtModules (#781)Jack Koenig
2018-04-02CyclicException identifies a problem node. (#778)Chick Markley
2018-03-28Enhance RenameMap to support circuit renaming (#775)Jack Koenig
2018-03-28Replace unconnected registers with 0 in Constant Propagation (#776)Jack Koenig
2018-03-27Change throwInternalError to use a String instead of Option[String] (#777)Jack Koenig
2018-03-27Const prop improvement (#772)Jack Koenig
2018-03-26Make WiringTransform remove its used annotations (#774)Schuyler Eldridge
2018-03-23Make Register Update Flattening a Transform and Delete Dangling Nodes (#692)Jack Koenig
2018-03-22Better bad annotation file error reporting (#771)Jack Koenig
2018-03-21GroupModule Transform (#766)Adam Izraelevitz
2018-03-21Add SyntaxErrorsException as a type of ParserException (#770)Jack Koenig
2018-03-19Adding the firrtl proto. (#746)Kevin Townsend
2018-03-19Pass up annotations in return value from Driver.execute (#760)Chick Markley
2018-03-19Masks for zero-width fields of mems should be width zero. (#763)grebe
2018-03-02Reduce Statement nesting in Wiring Pass (#751)Jack Koenig
2018-03-02Fix annotation deserialization of component subfields (#750)Jack Koenig
2018-03-01[name change] Use LsbLargerThanMsbException (#740)Schuyler Eldridge
2018-02-27Refactor Annotations (#721)Jack Koenig
2018-02-27Add log-level debug message for modules that get deduped (#748)Jack Koenig
2018-02-26Rename loadAnnotations -> getAnnotations (#747)Jack Koenig
2018-02-23Add graph summation "+" to DiGraph (#744)Schuyler Eldridge
2018-02-22Add tests for #702. Adds Utility functions. Allows clock muxing in FIRRTL, bu...Adam Izraelevitz
2018-02-21Change primop arg type (#587)Adam Izraelevitz
2018-02-16Replacematcherror - catch exceptions and convert to internal error. (#424)Jim Lawson
2018-02-08CheckHighForm should check that Bits MSB >= LSB (#738)Schuyler Eldridge
2018-02-07Fix EulerTour for circuits with one module (#736)Schuyler Eldridge
2018-02-05Added comments to ExpandWhens (#716)Adam Izraelevitz
2018-01-30Make Constant Propagation respect dontTouch on registersJack Koenig
2018-01-30Fix bug incorrectly propagating constants on submodule inputsJack Koenig
2018-01-15WiringTransform Refactor (#648)Schuyler Eldridge
2018-01-08Typo: ExecutionOptionManager -> ExecutionOptionsManager.Leway Colin
2018-01-05Fix FirrtlExecutionOptions backward incompatible change (#704). (#720)Jim Lawson
2018-01-05Remove erroneous undef of RANDOMIZE in emitted VerilogJack Koenig
2017-12-29Add support for multiple annotation filesJack
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