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authorAdam Izraelevitz2018-05-09 10:19:45 -0700
committerGitHub2018-05-09 10:19:45 -0700
commit77cfdbf05cafa78946a5684a0e4a530ebecd6547 (patch)
tree6b0a4d288cb5adb518b3b9e09d3762fb93c050f7 /src
parent227a523c327c63144544312aab01c164a67c2a94 (diff)
Bugfix: ports of a temporary name would break const-prop (#806)
Diffstat (limited to 'src')
-rw-r--r--src/main/scala/firrtl/transforms/ConstantPropagation.scala2
-rw-r--r--src/test/scala/firrtlTests/ConstantPropagationTests.scala17
2 files changed, 18 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/transforms/ConstantPropagation.scala b/src/main/scala/firrtl/transforms/ConstantPropagation.scala
index c417357b..60d9ac2c 100644
--- a/src/main/scala/firrtl/transforms/ConstantPropagation.scala
+++ b/src/main/scala/firrtl/transforms/ConstantPropagation.scala
@@ -347,7 +347,7 @@ class ConstantPropagation extends Transform {
// When propagating a reference, check if we want to keep the name that would be deleted
def propagateRef(lname: String, value: Expression): Unit = {
value match {
- case WRef(rname,_,_,_) if betterName(lname, rname) && !swapMap.contains(rname) =>
+ case WRef(rname,_,kind,_) if betterName(lname, rname) && !swapMap.contains(rname) && kind != PortKind =>
assert(!swapMap.contains(lname)) // <- Shouldn't be possible because lname is either a
// node declaration or the single connection to a wire or register
swapMap += (lname -> rname, rname -> lname)
diff --git a/src/test/scala/firrtlTests/ConstantPropagationTests.scala b/src/test/scala/firrtlTests/ConstantPropagationTests.scala
index c798ba37..19fe20c9 100644
--- a/src/test/scala/firrtlTests/ConstantPropagationTests.scala
+++ b/src/test/scala/firrtlTests/ConstantPropagationTests.scala
@@ -1030,4 +1030,21 @@ class ConstantPropagationIntegrationSpec extends LowTransformSpec {
|""".stripMargin
execute(input, check, Seq.empty)
}
+
+ "Temporary named port" should "not be declared as a node" in {
+ val input =
+ """circuit Top :
+ | module Top :
+ | input _T_61 : UInt<1>
+ | output z : UInt<1>
+ | node a = _T_61
+ | z <= a""".stripMargin
+ val check =
+ """circuit Top :
+ | module Top :
+ | input _T_61 : UInt<1>
+ | output z : UInt<1>
+ | z <= _T_61""".stripMargin
+ execute(input, check, Seq.empty)
+ }
}