| Age | Commit message (Expand) | Author |
|---|
| 2015-07-30 | Updated error and feature tests. Fixed bug in detecting incorrect genders | azidar |
| 2015-07-30 | Added eqv for bitwise equality, and change eq to be arithmetic equality | azidar |
| 2015-07-30 | Added primitive linking to firrtl-test-main | azidar |
| 2015-07-30 | Started adding linking support | azidar |
| 2015-07-30 | Updated lots of tests so they pass. Found one bug in expand whens | azidar |
| 2015-07-29 | Added linux zip | Adam Izraelevitz |
| 2015-07-29 | Finished supporting Chisel 2.0 Ref Chip | Adam Izraelevitz |
| 2015-07-29 | Add bigint support. | Adam Izraelevitz |
| 2015-07-28 | Integrated bigint. Mostly works, but getting "cast" error for make Test. | Adam Izraelevitz |
| 2015-07-22 | Fixed verilog so it emits non-random inital values. Changed Not to be | Adam Izraelevitz |
| 2015-07-21 | Firrtl generates verilog that compiles, but does not work | Adam Izraelevitz |
| 2015-07-21 | Fixed bug in fix :P | azidar |
| 2015-07-21 | Fixed removing non-referenced components | azidar |
| 2015-07-21 | Made things go faster. Still in progress. Expand when now removes | Adam Izraelevitz |
| 2015-07-17 | Datapath compiles with Chisel 2.0 -> FIRRTL -> Verilog! | Adam Izraelevitz |
| 2015-07-16 | Merge branch 'new-low-firrtl' of github.com:ucb-bar/firrtl into new-low-firrtl | azidar |
| 2015-07-16 | Fixed rename to work with chisel3 stuff | azidar |
| 2015-07-14 | Fixed performance bug in backend. Added renaming | azidar |
| 2015-07-14 | Added tests for clocks. Added remove scope and special chars passes. Added te... | azidar |
| 2015-07-14 | Added clock support | azidar |
| 2015-07-14 | Updated flo backend | azidar |
| 2015-07-14 | Passes riscv-mini tests | azidar |
| 2015-07-14 | Pass most tests. The ones that do not pass are not expected to, yet | azidar |
| 2015-07-14 | Still partial commit, many tests pass. Many tests fail. | azidar |
| 2015-07-14 | Partial commit | azidar |
| 2015-07-14 | In progress commit | azidar |
| 2015-07-14 | Fixed bug in lowering, where the indexes to many-connects and accessors weren... | azidar |
| 2015-07-13 | Added tests for clocks. Added remove scope and special chars passes. Added te... | azidar |
| 2015-07-10 | Added clock support | azidar |
| 2015-07-07 | Updated flo backend | azidar |
| 2015-07-07 | Passes riscv-mini tests | azidar |
| 2015-07-07 | Pass most tests. The ones that do not pass are not expected to, yet | azidar |
| 2015-07-06 | Still partial commit, many tests pass. Many tests fail. | azidar |
| 2015-07-06 | Partial commit | azidar |
| 2015-07-06 | In progress commit | azidar |
| 2015-07-06 | Updated todo | azidar |
| 2015-07-02 | Added firrtl-lexer | azidar |
| 2015-07-02 | Fixed performance bugs, runs 7x faster | azidar |
| 2015-07-02 | Fixed stanza, optimize works, added a time printout | azidar |
| 2015-07-02 | Hopefully fixed stanza so it can correctly compile itself | azidar |
| 2015-07-01 | Updated TODO. | azidar |
| 2015-06-12 | Major revisions to spec. Bumped to v0.1.2 | azidar |
| 2015-06-05 | Added updated stanza | azidar |
| 2015-06-05 | Commited most recent pdf | azidar |
| 2015-06-04 | Fixed fir files so they correctly compile to verilog! Front-end needs to gene... | azidar |
| 2015-06-04 | Added Adam's changes to stanza | azidar |
| 2015-06-03 | Fixed verilog backend bugs. Passes ALU. Fails Datapath | azidar |
| 2015-06-02 | Added low firrtl check. Corrected bug in prefix matching in high firrtl check | azidar |
| 2015-06-02 | Changed Core.fir so dshl wasn't huge. Fixed padding pass to preserve correct ... | azidar |
| 2015-06-02 | Merge branch 'master' of github.com:ucb-bar/firrtl | azidar |
