Passes riscv-mini tests

2 files changed, 19 insertions, 5 deletions

diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index b500f991..ed3f0079 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -1908,7 +1908,7 @@ defn split-exp (c:Circuit) :
          (s:Begin) : 
             do(f,s)
          (s:Conditionally) : 
-            add(v,map(split-exp-e{_,false,info(s)},s))
+            add(v,map(split-exp-e{_,full-name(loc(conseq(s) as Connect)),info(s)},s))
             do(f,s)
          (s:Connect) :
             match(loc(s)) :
@@ -2089,6 +2089,10 @@ defn pad-widths-s (s:Stmt) -> Stmt :
          val i = int-width!(type(value(s)))
          val exp* = pad-widths-e(i,value(s))
          DefNode(info(s),name(s),exp*)
+      (s:Conditionally) : 
+         val i = int-width!(type(pred(s)))
+         val pred* = pad-widths-e(i,pred(s))
+         Conditionally(info(s),pred*,conseq(s),alt(s))
       (s) : s
 
 public defn pad-widths (c:Circuit) -> Circuit :
diff --git a/src/main/stanza/verilog.stanza b/src/main/stanza/verilog.stanza
index 0367c333..1904f92f 100644
--- a/src/main/stanza/verilog.stanza
+++ b/src/main/stanza/verilog.stanza
@@ -140,13 +140,16 @@ defn get-name (e:Expression) -> Symbol :
       (e) : error("Shouldn't be here")
 
 defn emit-module (m:InModule) :
+   val vdecs = Vector<KeyValue<Symbol,Stmt>>() ; all declarations
    val decs = HashTable<Symbol,Stmt>(symbol-hash) ; all declarations
    val cons = HashTable<Symbol,Expression>(symbol-hash) ; all connections
    val ens = HashTable<Symbol,Expression>(symbol-hash) ; all enables
    defn build-table (m:InModule) :
       defn build-table (s:Stmt) -> Stmt :
          match(map(build-table,map(remove-subfield,s))) : 
-            (s:DefWire|DefRegister|DefAccessor|DefMemory|DefNode|DefInstance) : decs[name(s)] = s
+            (s:DefWire|DefRegister|DefAccessor|DefMemory|DefNode|DefInstance) : 
+               add(vdecs,name(s) => s)
+               decs[name(s)] = s
             (s:Conditionally) : 
                val n = get-name(loc(conseq(s) as Connect))
                ens[n] = pred(s)
@@ -169,7 +172,7 @@ defn emit-module (m:InModule) :
 
    val sh = get-sym-hash(m)
 
-   for x in decs do :
+   for x in vdecs do :
       val sym = key(x)
       match(value(x)) :
          (s:DefWire) :
@@ -198,6 +201,8 @@ defn emit-module (m:InModule) :
                val n* = to-symbol $ string-join $ [sym "_" name(f)]
                add(wires,["wire " get-width(type(f)) " " n* ";"])
                add(inst-ports[sym], ["." name(f) "( " n* " )"])
+               if flip(f) == REVERSE :
+                  add(assigns,["assign " n* " = " emit(cons[n*]) ";"])
          (s:DefAccessor) : 
             switch {_ == acc-dir(s)} :
                READ :
@@ -210,9 +215,11 @@ defn emit-module (m:InModule) :
                      add(updates,[name(index*) " <= " emit(index(s)) ";"])
 
                      ; emit read accessor
+                     add(wires,["wire " get-width(type(type(source(s)) as VectorType)) " " sym ";"])
                      add(assigns,["assign " sym " = " emit(source(s)) "[" emit(index*) "];"])
                   else :
                      ; emit read accessor
+                     add(wires,["wire " get-width(type(type(source(s)) as VectorType)) " " sym ";"])
                      add(assigns,["assign " sym " = " emit(source(s)) "[" emit(index(s)) "];"])
                WRITE : 
                   if key?(ens,sym) :
@@ -231,8 +238,11 @@ defn emit-module (m:InModule) :
          if length(ports(m)) - 1 == i :
             end = "\n);\n"
          switch {_ == direction(p)} :
-            INPUT  : print-all([port-indent "input  " get-width(type(p)) " " name(p) end])
-            OUTPUT : print-all([port-indent "output " get-width(type(p)) " " name(p) end])
+            INPUT  : 
+               print-all([port-indent "input  " get-width(type(p)) " " name(p) end])
+            OUTPUT : 
+               print-all([port-indent "output " get-width(type(p)) " " name(p) end])
+               add(assigns,["assign " name(p) " = " emit(cons[name(p)]) ";"])
 
    for w in wires do :
       print("  ")