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2018-08-29Filter resource file names to avoid including the same file multiple times. ↵Jim Lawson
(#883) * Filter resource file names to avoid including the same file multiple times. Addresses issue #882. * Use a Set instead of a Map to filter Verilog files. * Use canonical paths for file name comparison and unify name generation. Provide a common method for copying resources to a directory to ensure the same resource ends up with the same name if it's copied by multiple clients. * Reduce confusion - another absolute -> canonical switch. Use the canonical path on the verilator command line for the filter additional Verilog sources.
2018-08-24Update DontTouchAnnotation not found error message (#864)Jack Koenig
2018-08-23Fix NoDedupMem to be cognizant of Module scope (#876)Jack Koenig
Previously, mems marked no dedup would prevent mems with the same instance name in other modules from deduping
2018-08-23Add LogLevel apply for String => LogLevel.ValueSchuyler Eldridge
This adds an apply method to the LogLevel object for conversion from a String to a LogLevel.value. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-08-21Allow the #delay before random initialization to be overriddenAndrew Waterman
The default of 0.002 can be less than the Verilog time precision, which effectively causes it to be rounded down to 0. So, allow the user to `define RANDOMIZE_DELAY to some other value. If the macro is not defined, the old behavior is preserved.
2018-08-17Binding support (#854)Chick Markley
- Fixed edge case file name that starts with . and has no suffix
2018-08-14Add targetDirName test (#869)Leway Colin
2018-08-10allowing overrides to $random (#859)Deborah Soung
2018-08-08Use LinkedHashSet in propagateAnnotations (#855)albertchen-sifive
Fixes #780
2018-08-07Make RemoveWires properly include registers in dependency graphJack Koenig
Fixes a bug where registers could be instantiated after nodes that referred to them Also add WRef.apply utility for nodes
2018-07-26Support for load memory annotations in chisel (#833)Chick Markley
* Support for load memory annotations in chisel This PR * Delays the BlackBoxSourceHelper transformation to the Emitter stage of the VerilogCompiler * remove from VerilogCompiler * move to VerilogEmitter * Changes the verilog emitter to allow programmatic access to the verilog module declaration * Creating a bindable module requires headers to match * Provides a unit test that shows how to generate a bindable module. * Binding support Treadle needed LoadMemoryAnnotation to be in firrtl instead of chisel in order to recognize the annotations and use them for memory loading * Binding support - Fixed bug that handled suffixes on memory initializing files * Binding support - Add a bit more doc to the API provided by the VerilogRenderer
2018-07-20Constant prop add (#849)albertchen-sifive
* add FoldADD to const prop, add yosys miter tests * add option for verilog compiler without optimizations * rename FoldLogicalOp to FoldCommutativeOp * add GetNamespace and RenameModules, GetNamespace stores namespace as a ModuleNamespaceAnnotation * add constant propagation for Tail DoPrims * add scaladocs for MinimumLowFirrtlOptimization and yosysExpectFalure/Success, add constant propagation for Head DoPrim * add legalize pass to MinimumLowFirrtlOptimizations, use constPropBitExtract in legalize pass
2018-07-11Make InstanceGraph have deterministic and use defined iteration order (#843)Jack Koenig
2018-07-10Fix bug in zero-width renaming (#845)Jack Koenig
Previously, Vecs of Bundles that contained a zero-width element would result in a ClassCastException
2018-07-10Combinational Dependency Annotation (#809)Adam Izraelevitz
2018-07-10InferWidths: improve performance (#846)edwardcwang
On circuits with large numbers of width inferences, prepend to a linked list instead of appending and having to make a copy. Fixes #842
2018-07-07Missing match on PassExceptions fixed. (#844)Chick Markley
This caused wrong message: "File a Firrtl Issue" Instead of the correct "Reference XX is not fully initialized"
2018-07-03Improve code generation for smem wmode and [w]mask ports (#834)Andrew Waterman
[skip formal checks] LEC passes with Formality * Improve code generation for smem RW-port wmode port A common case for these port-enables is wen = valid & write ren = valid & !write which the RW-port transform currently turns into en = (valid & write) | (valid & !write) wmode = valid & write because it proved `wen` and `ren` are mutually exclusive via `write`. Synthesis tools can trivially optimize `en` to `valid`, so that's not a problem, but the wmode field can't be optimized if going into a black box. This PR instead sets `wmode` to whatever node was used to prove mutual exclusion, which is always a simpler expression. In this case: en = (valid & write) | (valid & !write) wmode = write * In RemoveCHIRRTL, infer mask relative to port definition Previously, it was inferred relative to the memory definition causing the mask condition to be redundantly conjoined with the enable signal. Also enable ReplSeqMems to ignore all ValidIfs (not just on Clocks) to improve QoR.
2018-07-02Make ZeroWidth properly rename removed empty aggregates (#839)Jack Koenig
Fixes #756
2018-06-28Make CheckCombLoops find combinational nodes with self-edges (#837)Albert Magyar
2018-06-28Protobuf (#832)Jack Koenig
Add support for ProtoBuf serialization and deserialization * Add support for additional features in .proto description Features added: Info, Fixed[Type|Literal], AnalogType, Attach, Params * Add support for .pb input files This involves an API change where FIRRTL no longer implicitly adds .fir to input file names
2018-06-21Provide a ProcessLogger() ot capture all output in isCommandAvailable(). (#831)Jim Lawson
2018-06-21--infer-rw should take no argument (#829)Schuyler Eldridge
This fixes --infer-rw to not expect an argument. After the annotations refactor, no option was required, but some legacy code remained. This also updates the test cases to be more correct and not specify an option to --infer-rw. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-06-15Improve Parser and Visitor (#819)Jack Koenig
* Update Parser to use ANTLR CharStreams This removes some unnecessary object creation in String reading and manipulation * Remove two unnecessary traversals from Block construction in Visitor
2018-06-14Fix TopWiringTests use of /tmp. (#825)Jim Lawson
Relying on /tmp as a place for test output will fail on multiuser systems and may fail if multiple instances of tests are running for the same user.
2018-06-13Resolve register clock dependencies in RemoveWires (#823)Schuyler Eldridge
Candidate fix for #749 This adds DefRegister netlist ordering to RemoveWires Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-06-12Deprecate SingleStringAnnotation (#811)Jack Koenig
It does not provide anything over NoTargetAnnotation. Its existence suggests some significance so removing it for clarity.
2018-06-11Allow escaped single quotes in RawParams (#820)Richard Lin
Escape raw params using \'
2018-06-11Add utilities for UInt and SInt literals (#815)Jack Koenig
Also minor cleanup to literal construction in Visitor
2018-06-11Use attach to connect analogs when grouping (#805)Colin Schmidt
2018-06-08Add a blacklist option for paths (#810)Colin Schmidt
Useful if you want to find out how a node was reachable and you used a blacklist during the reachability analysis
2018-06-06Mechanism to stop verilator from generating VCD file Chisel Issue #808 (#794)Chick Markley
Add optional argument to verilogToCpp to suppress VCD
2018-06-06ConstProp attached wires if there is also a port (#818)Jack Koenig
This enables the pattern of attaching "through" a wire to give better Verilog that also works in Verilator Use WrappedExpression when combining attaches in ExpandWhens to ensure no duplication of references in resulting, combined attaches
2018-05-30Makes ExpandWhens preserve connect Infoschick
* Collects Infos found for symbols * Merges multiple sources for symbol into MultiInfo * Restores these Infos on connect statements. * Add test showing preserved Infos * Changed ++ methods on the Info sub-classes * Ignore NoInfo being added * Fixed way adding was implemented in MultiInfo * Made InfoMap a class which defines the default value function
2018-05-29Fix pad (#817)Jack Koenig
* Make VerilogEmitter properly handle pad of width <= width of arg * Constant prop pads with pad amount <= width of arg
2018-05-23Add Circuit as option to FirrtlOptions (#814)Jack Koenig
2018-05-21Fix more problems with zero width things. (#779)grebe
This should close #757. It should also allow for stop() and printf() to be used with zero-width fields.
2018-05-15Don't use bash to determine command availability - fixes #807 (#808)Jim Lawson
2018-05-15Replace truncating add and sub with addw/subw (#800)Jack Koenig
Replaces old VerilogWrap which didn't work with split expressions and was actually buggy anyway. This functionality reduces unnecessary intermediates in emitted Verilog.
2018-05-11TopWiring Transform (#798)alonamid
* top wiring transform * fixup comments * TopWiring cosmetics * move prefix into TopWiringAnnotation * remove test function from transform file * add ChildrenMap to InstanceGraph API * use namespaces * remove wiringUtils from TopWiring pass * enable multiple output functions * TopWiring cosmetics, tests and lowform
2018-05-09Bugfix: ports of a temporary name would break const-prop (#806)Adam Izraelevitz
2018-05-02Deprecate old WiringUtils methods/classes (#801)Schuyler Eldridge
The following are deprecated in favor of DiGraph/InstanceGraph: - firrtl.passes.wiring.Lineage - firrtl.passes.wiring.WiringUtils.ChildrenMap - firrtl.passes.wiring.WiringUtils.getChildrenMap - firrtl.passes.wiring.WiringUtils.getLineage Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-04-29Fix pathological behavior of Namespace for name collisions (#788)Jack Koenig
2018-04-26Fix bug in VerilogMemDelays (#795)Jack Koenig
* Change VerilogMemDelays to put new Statements at end of Module Fixes #547 This is instead of putting them right after the modified DefMemory which could result in use before declaration errors for things that feed into the new logic. * Adds tests that show VerilogMemDelays crashing. (#792)
2018-04-16Cleaning up BlackBoxSourceHelper - use absolute file paths. (#789)Jim Lawson
* Cleaning up BlackBoxSourceHelper - use absolute file paths. ```bash make[1]: *** No rule to make target `test_run_dir/examples.AccumBlackBox_PeekPokeTest_Verilator345491158/AccumBlackBox.v', needed by `/Users/john/chisel-testers/test_run_dir/examples.AccumBlackBox_PeekPokeTest_Verilator345491158/VAccumBlackBoxWrapper.h'. Stop. ``` since the path `test_run_dir/examples.AccumBlackBox_PeekPokeTest_Verilator345491158/AccumBlackBox.v` does not exist inside `test_run_dir`. We should either: - strip the targetDir prefix, - prepend a `../` to the path, - use absolute paths I decided to go with the latter since this makes the least assumptions about the actual downstream processing and we already use absolute paths in other parts of this code. * Minor cleanup. - Anonymize make failure comment. - Use common map syntax.
2018-04-13Remove infinitely recursive function (#790)Jack Koenig
h/t @sdtwigg
2018-04-11Cleaning up BlackBoxSourceHelper (#786)Henry Cook
Create sources once per module, not once per instance Clean up writing the file list Don't prepend file list with '-v's (non-standard and not all verilog) Change file list file name (not all verilog) Use ListSets for determinism
2018-04-11Make DiGraph.linearize be iterative instead of recursive (#785)Jack Koenig
Also make DiGraphTests more ScalaTest-y
2018-04-10Fix bug in Constant Propagation for registers propped to zero (#787)Jack Koenig
It wasn't properly padding the width of the constant zero. Also add a test that shows the buggy behavior.
2018-04-03Make Dedup properly dedup ExtModules (#781)Jack Koenig
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