diff options
| author | Colin Schmidt | 2018-06-11 11:46:50 -0700 |
|---|---|---|
| committer | Jack Koenig | 2018-06-11 11:46:50 -0700 |
| commit | 9bd639acf58ad3a6c13b858d65845a95ddac1610 (patch) | |
| tree | 6778c033a8b2799b42a07c9154f9252c1fe53b2c /src | |
| parent | b25658019b9fcdeca9081de0ba897befedf86375 (diff) | |
Use attach to connect analogs when grouping (#805)
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/firrtl/transforms/GroupComponents.scala | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/transforms/GroupComponents.scala b/src/main/scala/firrtl/transforms/GroupComponents.scala index 439a1642..55828e0a 100644 --- a/src/main/scala/firrtl/transforms/GroupComponents.scala +++ b/src/main/scala/firrtl/transforms/GroupComponents.scala @@ -181,7 +181,11 @@ class GroupComponents extends firrtl.Transform { def punchSignalOut(group: String, exp: Expression): String = { val portName = addPort(group, exp, Output) - groupStatements(group) += Connect(NoInfo, WRef(portName), exp) + val connectStatement = exp.tpe match { + case AnalogType(_) => Attach(NoInfo, Seq(WRef(portName), exp)) + case _ => Connect(NoInfo, WRef(portName), exp) + } + groupStatements(group) += connectStatement portName } |
