From 9bd639acf58ad3a6c13b858d65845a95ddac1610 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Mon, 11 Jun 2018 11:46:50 -0700 Subject: Use attach to connect analogs when grouping (#805) --- src/main/scala/firrtl/transforms/GroupComponents.scala | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/main/scala/firrtl/transforms/GroupComponents.scala b/src/main/scala/firrtl/transforms/GroupComponents.scala index 439a1642..55828e0a 100644 --- a/src/main/scala/firrtl/transforms/GroupComponents.scala +++ b/src/main/scala/firrtl/transforms/GroupComponents.scala @@ -181,7 +181,11 @@ class GroupComponents extends firrtl.Transform { def punchSignalOut(group: String, exp: Expression): String = { val portName = addPort(group, exp, Output) - groupStatements(group) += Connect(NoInfo, WRef(portName), exp) + val connectStatement = exp.tpe match { + case AnalogType(_) => Attach(NoInfo, Seq(WRef(portName), exp)) + case _ => Connect(NoInfo, WRef(portName), exp) + } + groupStatements(group) += connectStatement portName } -- cgit v1.2.3