diff options
| author | albertchen-sifive | 2018-08-08 15:17:13 -0700 |
|---|---|---|
| committer | Jack Koenig | 2018-08-08 15:17:13 -0700 |
| commit | 0ec4d84349a69b1c62a17d70e369abb91a35ce51 (patch) | |
| tree | 72a7245912aed87bdc32390b9b31aad157e5a999 /src | |
| parent | 0a2e2c2e4a97fb8d14e7259f779d8398e243e889 (diff) | |
Use LinkedHashSet in propagateAnnotations (#855)
Fixes #780
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/firrtl/Compiler.scala | 4 | ||||
| -rw-r--r-- | src/test/scala/firrtlTests/AnnotationTests.scala | 18 |
2 files changed, 20 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/Compiler.scala b/src/main/scala/firrtl/Compiler.scala index 603c05f6..b34782b5 100644 --- a/src/main/scala/firrtl/Compiler.scala +++ b/src/main/scala/firrtl/Compiler.scala @@ -283,8 +283,8 @@ abstract class Transform extends LazyLogging { resAnno: AnnotationSeq, renameOpt: Option[RenameMap]): AnnotationSeq = { val newAnnotations = { - val inSet = inAnno.toSet - val resSet = resAnno.toSet + val inSet = mutable.LinkedHashSet() ++ inAnno + val resSet = mutable.LinkedHashSet() ++ resAnno val deleted = (inSet -- resSet).map { case DeletedAnnotation(xFormName, delAnno) => DeletedAnnotation(s"$xFormName+$name", delAnno) case anno => DeletedAnnotation(name, anno) diff --git a/src/test/scala/firrtlTests/AnnotationTests.scala b/src/test/scala/firrtlTests/AnnotationTests.scala index b2aeda77..10414786 100644 --- a/src/test/scala/firrtlTests/AnnotationTests.scala +++ b/src/test/scala/firrtlTests/AnnotationTests.scala @@ -625,4 +625,22 @@ class JsonAnnotationTests extends AnnotationTests with BackendCompilationUtiliti if msg.contains("JObject") => } } + + object DoNothingTransform extends Transform { + override def inputForm: CircuitForm = UnknownForm + override def outputForm: CircuitForm = UnknownForm + + protected def execute(state: CircuitState): CircuitState = state + } + + "annotation order" should "should be preserved" in { + val annos = Seq(anno("a"), anno("b"), anno("c"), anno("d"), anno("e")) + val input: String = + """circuit Top : + | module Top : + | input a : UInt<1> + | node b = c""".stripMargin + val cr = DoNothingTransform.runTransform(CircuitState(parse(input), ChirrtlForm, annos)) + cr.annotations.toSeq shouldEqual annos + } } |
